IS62WV12816DALL Datasheet, PDF (14/17 Pages) Integrated Silicon Solution, Inc – 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62WV12816DALL/DBLL, IS65WV12816DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
Test Condition
Min. Max. Unit
Vdr
Vdd for Data Retention
See Data Retention Waveform
1.5 3.6
V
Idr
Data Retention Current
Vdd = 1.5V,
CS1 ≥ Vdd – 0.2V,
CS2 ≥ Vdd – 0.2V, or
0V ≤ CS2 ≤ 0.2V, 0V ≤ Vin
Com.
—
4
µA
Ind.
—
6
µA
Auto.
—
15
µA
typ.⁽²⁾
2
µA
tsdr
Data Retention Setup Time See Data Retention Waveform
0
—
ns
trdr
Recovery Time
See Data Retention Waveform
trc
—
ns
Note:
1. In data retention mode, CS2 controls the address, WE, CS1, OE, and the Din buffer. If CS2 controls data retention mode, Vin (for
these inputs) can be in the high impedance state. If CS1 controls the data retention mode, CS2 must satisfy either CS2 ≥ Vcc –
0.2 V or CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
2. Typical values are measured at Vdd = Vdr(min), Ta = 25^oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1 Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CS1
GND
CS1 ≥ VDD - 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
VDD
CS2
tSDR
tRDR
VDR
CS2 ≤ 0.2V
GND
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
  Rev.  A
08/16/2011