IS61QDB22M18 Datasheet, PDF (9/27 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 8.
Operation
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write All Bytes
Abort Write
K(t)
L→H
L→H
L→H
L→H
L→H
L→H
K
(t + 0.5)
L→H
L→H
L→H
L→H
L→H
L→H
BW₀
L
H
H
H
L
H
L
H
H
H
L
H
BW₁
H
L
H
H
L
H
H
L
H
H
L
H
BW₂
H
H
L
H
L
H
H
H
L
H
L
H
BW₃
H
H
H
L
L
H
H
H
H
L
L
H
D_B
D0-8 (t)
D9-17 (t)
D18-26 (t)
D27-35 (t)
D0-35 (t)
Don’t care
D_B+1
D0-8 (t + 0.5)
D9-17 (t + 0.5)
D18-26 (t + 0.5)
D27-35 (t + 0.5)
D0-35 (t + 0.5)
Don’t care
Notes;
1. For all cases. W must be active low during the rising edge of K occurring at time t.
2. For timing definitions, refer to the AC Characteristics on page 16. Signals must have AC specifications with respect to switching
clocks K and K.
X18 Write Truth Table (Use this table with the Timing Reference Diagram for Truth Table on page 8.)
Operation
Write Byte 0 on B
Write Byte 1 on B
Write All Bytes on B
Abort Write on B
Write Byte 1 on B+1
Write Byte 2 on B+1
Write All Bytes on B+1
Abort Write on B+1
K(t)
L→H
L→H
L→H
L→H
K
(t + 0.5)
L→H
L→H
L→H
L→H
BW₀
L
H
L
H
L
H
L
H
BW₁
H
L
L
H
H
L
L
H
D_B
D0–8 (t)
D9–17 (t)
D0–17 (t)
Don’t care
D_B+1
D0–8(t + 0.5)
D9–17(t + 0.5)
D0–17(t + 0.5)
Don’t care
Notes;
1. Refer to Timing Reference Diagram for Truth Table on page 8. Cycle time starts at n and is referenced to the K clock.
2. For all cases, W must be active low during the rising edge of K occurring at t.
3. For timing definitions, refer to the AC Characteristics on page 16. Signals must have AC specs with respect to switching clocks K
and K.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
06/29/06