IS61QDB22M18 Datasheet, PDF (17/27 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
Read and Deselect Cycles Timing Diagram
Read
t_KLKH
t_KHKH
t_KHKL
Read
K
t_KHKH
K
SA
A1
A2
t_IVKH t_KHIX
R
Q (Data Out)
C
C
t_KHKH
t_KHKL
t_KLKH
t_CHQX
t_KLKH
CQ
t_CHCQX
CQ
NOP
Read
NOP
t_AVKH
t_KHAX
A3
Q1-1 Q1-2 Q2-1
t_CHQV
t_CHQX
Q2-2
t_CHQZ
t_CHQV
t_CQHQV
t_CHCQV
t_CHCQX
t_CQHQX
t_CHCQV
Q3-1
Don’t Care
Undefined
Notes: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 (that is, the next internal
burst address following A1+0).
2. Outputs are disabled one cycle after an NOP.
Integrated Silicon Solution, Inc. — 1-800-379-4774
17
Rev. B
06/29/06