IS61QDB22M18 Datasheet, PDF (20/27 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.
Signal List
• TCK: test clock
• TMS: test mode select
• TDI: test data-in
• TDO: test data-out
JTAG DC Operating Characteristics (T_A = 0 to +70° C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter
Symbol
Minimum
JTAG input high voltage
JTAG input low voltage
JTAG output high level
JTAG output low level
V_IH1
V_IL1
V_OH1
V_OL1
1.3
-0.3
V_DD-0.4
V_SS
1. All JTAG inputs and outputs are LVTTL-compatible.
2. I_OH1 ≥ -|2mA|
3. I_OL1 ≥ +|2mA|.
Typical
—
—
—
—
Maximum
V_DD+0.3
0.5
V_DD
0.4
Units
V
V
V
V
Notes
1
1
1, 2
1, 3
JTAG AC Test Conditions (T_A = 0 to +70° C, V_DD = 1.8V -5%, +5%)
Parameter
Symbol
Input pulse high level
V_IH1
Input pulse low level
V_IL1
Input rise time
T_R1
Input fall time
T_F1
Input and output timing reference level
Conditions
1.3
0.5
1.0
1.0
0.9
Units
V
V
ns
ns
V
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
06/29/06