IS61QDB22M18 Datasheet, PDF (3/27 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
Pin Description
Symbol
Pin Number
Description
K, K
6B, 6A
Input clock.
C, C
6P, 6R
Input clock for output data control.
CQ, CQ
11A, 1A
Output echo clock.
Doff
1H
DLL disable when low.
SA
9A, 4B, 8B, 5C, 6C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R, 8R, 9R
1M x 36 address inputs.
SA
3A, 9A, 4B, 8B, 5C, 6C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R,
5R, 7R, 8R, 9R
2M x 18 address inputs.
D0–D8
D9–D17
D18–D26
D27–D35
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P
1M x 36 data inputs.
Q0–Q8
Q9–Q17
Q18–Q26
Q27–Q35
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P
1M x 36 data outputs.
D0–D8
D9–D17
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
2M x 18 data inputs.
Q0–Q8
Q9–Q17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 2D, 3E, 2F, 3G, 2K, 2L, 3N, 3P
2M x 18 data outputs.
W
4A
Write control, active low.
R
8A
Read control, active low.
BW_0, BW_1, BW_2, BW₃ 7B, 7A, 5A,5B
1M x 36 byte write control, active low.
BW_0, BW₁
7B, 5A
2M x 18 byte write control, active low.
V_REF
2H, 10H
Input reference level.
V_DD
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
Power supply.
V_DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output power supply.
V_SS
2A, 10A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 8M, 4N, 8N
Power supply.
ZQ
11H
Output driver impedance control.
TMS, TDI, TCK
10R, 11R, 2R
IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).
TDO
1R
IEEE 1149.1 test output (1.8V LVTTL level).
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
06/29/06