IS61QDB22M18 Datasheet, PDF (15/27 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
AC Characteristics (T_A = 0 to + 70C, V_DD = 1.8V -5%, +5%)
Parameter
Symbol
30
(333MHz)
Min
Max
Units
Notes
Clock
Cycle time (K, K, C, C)
t_KHKH
Clock phase jitter (K, K, C, C)
t_KC-VAR
Clock high pulse (K, K, C, C)
t_KHKL
Clock low pulse (K, K, C, C)
t_KLKH
Clock to clock (K_H>K_H, C_H>C_H)
t_KHKH
Clock to data clock (K_H>C_H, K_H>C_H) t_KHCH
DLL lock (K, C)
t_KC-lock
K static to DLL reset
t_KC-reset
Output Times
3.0
1.2
1.2
1.35
0.0
1024
30
4.0
0.12
1.35
ns
ns
ns
ns
ns
ns
cycle
cycle
C, C high to output valid
C, C high to output hold
C, C high to echo clock valid
C, C high to echo clock hold
CQ, CQ high to output valid
CQ, CQ high to output hold
C high to output high-Z
C high to output low-Z
Setup Times
t_CHQV
0.40
ns
1, 3
t_CHQX
-0.40
ns
1, 3
t_CHCQV
0.35
ns
3
t_CHCQX -0.35
ns
3
t_CQHQV
0.25
ns
1, 3
t_CQHQX -0.25
ns
1, 3
t_CHQZ
0.33
ns
1, 3
t_CHQX1 -0.33
ns
1, 3
Address valid to K, K rising edge
t_AVKH
0.33
—
ns
2
Control inputs valid to K rising edge t_IVKH
0.33
—
ns
2
Data-in valid to K, K rising edge
t_DVKH
0.33
—
ns
2
Hold Times
K rising edge to address hold
t_KHAX
0.33
—
ns
2
K rising edge to control inputs hold
t_KHIX
0.33
—
ns
2
K, K rising edge to data-in hold
t_KHDX
0.33
—
ns
2
1. See AC Test Loading on page 15.
2. During normal operation, V_IH, V_IL, T_RISE, and T_FALL of inputs must be within 20% of V_IH, V_IL, T_RISE, and T_FALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. B
06/29/06