IS64C6416 Datasheet, PDF (8/12 Pages) Integrated Silicon Solution, Inc – high-speed, 1,048,576-bit static RAM

IS64C6416
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
-15
-20
Min. Max. Min. Max. Unit
tWC Write Cycle Time
15 —
20 —
ns
tSCE CE to Write End
10 —
12 —
ns
tAW Address Setup Time
to Write End
10 —
12 —
ns
tHA Address Hold from Write End 0 —
0—
ns
tSA Address Setup Time
0—
0—
ns
tPWB LB, UB Valid to End of Write 10 —
12 —
ns
tPWE1 WE Pulse Width (OE =High) 10 —
12 —
ns
tPWE2 WE Pulse Width (OE=Low) 10 —
12 —
ns
tSD Data Setup to Write End
7—
9—
ns
tHD Data Hold from Write End
0—
0—
ns
tHZWE⁽²⁾ WE LOW to High-Z Output —
7
—9
ns
tLZWE⁽²⁾ WE HIGH to Low-Z Output
3
—
3—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input
pulse levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals
must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The
Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
01/07/03