IS64C6416 Datasheet, PDF (10/12 Pages) Integrated Silicon Solution, Inc – high-speed, 1,048,576-bit static RAM

IS64C6416
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
t WC
VALID ADDRESS
OE
ISSI ^®
t HA
CE ^LOW
WE
t SA
UB, LB
DOUT
DATA UNDEFINED
DIN
t AW
t PWE1
t PBW
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CEWR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ⁽¹⁾
ADDRESS
OE ^LOW
t WC
VALID ADDRESS
t HA
CE _LOW
WE
UB, LB
t SA
DOUT
DATA UNDEFINED
DIN
t AW
t PWE2
t PBW
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CEWR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
01/07/03