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IS61LV6416 Datasheet, PDF (7/16 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY | |||
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IS61LV6416
IS61LV6416L
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
-8 ns
Min. Max.
8â
6â
8â
-10 ns
Min. Max.
10 â
8â
8â
-12 ns
Min. Max.
12 â
9â
9â
Unit
1
ns
ns
ns
2
tHA
Address Hold from Write End
0â
0â
0â
ns
tSA
Address Setup Time
tPBW
LB, UB Valid to End of Write
0â
7â
0â
8â
0â
9â
ns
3
ns
tPWE1/tPWE2 WE Pulse Width (OE = HIGH/LOW)
6â
8â
9â
ns
tSD
Data Setup to Write End
tHD
Data Hold from Write End
6â
0â
6â
0â
6â
0â
ns
4
ns
tHZWE(2)
tLZWE(2)
WE LOW to High-Z Output
WE HIGH to Low-Z Output
â4
3â
â5
3â
â6
3â
ns
ns
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
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initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
7
8
9
10
11
12
Integrated Silicon Solution, Inc.
7
Rev. I
11/22/05
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