IS61LV6416 Datasheet, PDF (10/16 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY

IS61LV6416
IS61LV6416L
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write)^(1,3)
t WC
t WC
ADDRESS
ADDRESS 1
ADDRESS 2
ISSI ^®
OE
t SA
CE _LOW
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc.
Rev. I
11/22/05