IS61LV6416 Datasheet, PDF (5/16 Pages) Integrated Circuit Solution Inc – 64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY

IS61LV6416
IS61LV6416L
ISSI ^®
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
1
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1a and 1b
2
AC TEST LOADS
3.3V
319 Ω
OUTPUT
30 pF
Including
jig and
scope
Figure 1a.
353 Ω
3
319 Ω
3.3V
4
OUTPUT
5 pF
353 Ω
5
Including
jig and
scope
6
Figure 1b.
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-8 ns
-10 ns
-12 ns
Min. Max. Min. Max. Min. Max.
Unit
tRC
Read Cycle Time
8—
10 —
12 —
ns
tAA
Address Access Time
—8
— 10
— 12
ns
tOHA
Output Hold Time
3—
3—
3—
ns
tACE
CE Access Time
—8
— 10
— 12
ns
tDOE
OE Access Time
—5
—5
—6
ns
tHZOE⁽²⁾
OE to High-Z Output
—5
—5
—6
ns
tLZOE⁽²⁾
OE to Low-Z Output
0—
0—
0—
ns
tHZCE⁽²
CE to High-Z Output
04
05
06
ns
tLZCE⁽²⁾
CE to Low-Z Output
3—
3—
3—
ns
tBA
LB, UB Access Time
—6
—6
—6
ns
tHZB
LB, UB to High-Z Output
04
05
06
ns
tLZB
LB, UB to Low-Z Output
0—
0—
0—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
7
8
9
10
11
12
Integrated Silicon Solution, Inc.
5
Rev. I
11/22/05