IS61QDP2B22M18A Datasheet, PDF (4/33 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1 /A2
SRAM Features description
Block Diagram
36 (18)
D (Data-In)
Data
Register
19 (20)
Address
Address
Register
19 (20)
R#
W#
BWx#
4 (2)
Control
Logic
36 (18) 36 (18)
Write
Driver
1M x 36
(2M x 18)
Memory Array
72 (36) _Output 72 (36)
Register
36 (18)
Q (Data-out)
2
CQ, CQ#
(Echo Clocks)
K
K#
C
C#
Doff#
Clock
Generator
Select Output Control
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R# in active low state
at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to
complete the burst of two in DDR mode. A set of free-running echo clocks, CQ and CQ#, are produced internally with
timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
The data corresponding to the first address is clocked two cycles later by the rising edge of the K# clock. The data
corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock.
A NOP operation (R# is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every rising edge of the K clock with first data whenever W# is low. The write
address is provided half cycle with second data later, registered by the rising edge of K#, so the write always occurs in
bursts of two.
The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented half cycle before the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#.
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array
on the third write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read
address followed by the same write address produces the latest write data. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).
Integrated Silicon Solution, Inc.- www.issi.com
4
Rev. B
10/02/2014