IS61QDP2B22M18A Datasheet, PDF (24/33 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1 /A2
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the
operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to
ensure that TDO comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the
TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
This register is loaded during the update-IR state of the TAP controller. Three-bit instructions can be serially loaded
into the instruction register. At power-up, the instruction register is loaded with the IDCODE instruction. It is also
loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary “01” pattern to allow for fault
isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. It is to skip certain chips
without serial boundary scan. This allows data to be shifted through the SRAM with minimal delay. The bypass register
is set LOW (V_SS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and output balls on the SRAM. Several No Connected(NC)
balls are also included in the scan register to reserve other product options. The boundary scan register is loaded with
the contents of the SRAM input and output ring when the TAP controller is in the capture-DR state and is then placed
between the TDI and TDO balls when the controller is moved to the shift-DR state. The EXTEST, SAMPLE/PRELOAD,
and SAMPLE Z instructions can be used to capture the contents of the input and output ring. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command
is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP
controller is in the shift-DR state. The ID register has a vendor ID code and other information
TAP Instruction Set
TAP Instruction Set is available to set eight instructions with the three bit instruction register and all combinations are
listed in the TAP Instruction Code Table. Three of listed instructions on this table are reserved and must not be used.
Instructions are loaded serially into the TAP controller during the Shift-IR state when the instruction register is placed
between TDI and TDO. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places
the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when
the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-
up or whenever the TAP controller is given a test logic reset state.
Integrated Silicon Solution, Inc.- www.issi.com
24
Rev. B
10/02/2014