IS61QDP2B22M18A Datasheet, PDF (20/33 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1 /A2
AC Timing Characteristics
(Over the Operating Temperature Range, V_DD=1.8V±5%, V_DDQ=1.5V/1.8V)
Parameter
Clock
Clock Cycle Time (K, K#,C,C#)
Clock Phase Jitter (K, K#,C,C#)
Clock High Time (K, K#,C,C#)
Clock Low Time (K, K#,C,C#)
Clock to Clock (K_H→ K#_H, C_H→ C#_H)
Clock to Data Clock (K > C, K# > C#)
DLL Lock Time (K,C)
Doff Low period to DLL reset
K static to DLL reset
Output Times
C,C# High to Output Valid
C,C# High to Output Hold
C,C# High to Echo Clock Valid
C,C# High to Echo Clock Hold
CQ, CQ# High to Output Valid
CQ, CQ# High to Output Hold
C,C# High to Output High-Z
C,C# High to Output Low-Z
Setup Times
Address valid to K rising edge
R#,W# control inputs valid to K rising
edge
BW_x# control inputs valid to K rising
edge
Data-in valid to K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to R#,W# control inputs
hold
K rising edge to BW_x# control inputs
hold
K, K# rising edge to data-in hold
Symbol
30 (333MHz)
Min Max
tKHKH
tKC var
tKHKL
tKLKH
tKHK#H
tKHCH
tKC lock
tDoffLowToReset
tKCreset
3.00
0.4
0.4
1.35
0
1024
5
30
8.4
0.3
1.35
tCHQV
tCHQX
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCHQZ
tCHQX1
tAVKH
tIVKH
tIVKH2
tDVKH
0.45
-
0.45
0.45
-
0.45
0.30
-
0.30
0.45
-
0.45
0.30
0.30
0.30
0.30
tKHAX
0.30
tKHIX
0.30
tKHIX2
0.30
tKHDX
0.30
33 (300MHz)
Min Max
3.33 8.4
0.3
0.4
0.4
1.50
0 1.48
1024
5
30
0.45
-
0.45
0.45
-
0.45
0.30
-
0.30
0.45
-
0.45
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
40 (250MHz)
Min Max
4.00 8.4
0.3
0.4
0.4
1.80
0
1.8
1024
5
30
0.45
-0.45
0.45
-0.45
0.30
-0.30
0.45
-0.45
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
unit
ns
ns
cycle
cycle
ns
ns
cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
notes
4
5
1,3
1,3
1
1
1,3
1,3
1,3
1,3
2
2
2
2
2
2
2
2
Notes:
1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R#, W#, BW₀#, BW₁# and (BW₂#, BW₃# for x36)
3. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. The data sheet parameters reflect tester guard bands and test setup variations.
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev. B
10/02/2014