IS61QDP2B22M18A Datasheet, PDF (25/33 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDP2B22M18A/A1/A2
IS61QDP2B21M36A/A1 /A2
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next
command is supplied during the Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a IEEE 1149.1 basic instruction which connects the boundary scan register between the TDI
and TDO pins when the TAP controller is in a Shift-DR state.. A snapshot of data on the inputs and output balls is
captured in the boundary scan register when the TAP controller is in a Shift-DR state. The user must be aware that the
TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates significantly faster.
Because there is a large difference between the clock frequencies, it is possible that during the capture-DR state, an
input or output will undergo a transition. The TAP may then try to capture a signal while in transition. This will not harm
the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To
ensure that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold time. The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the
boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the shift-
DR state. This places the boundary scan register between the TDI and TDO balls.
PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the
selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the bypass
register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a board.
PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
EXTEST
The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects
the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. IEEE Standard
1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan
register has a special bit located at bit #109. When this scan cell, called the “EXTEST output bus tri-state,” is latched
into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-
bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive
the output bus. When LOW, this bit places the output bus into a High Z condition. This bit can be set by entering the
SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell during the Shift-DR state.
During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST
instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.
JTAG DC Operating Characteristics
(Over the Operating Temperature Range, V_DD=1.8V±5%)
Parameter
Symbol
Min
JTAG Input High Voltage
JTAG Input Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
JTAG Output High Voltage
JTAG Output Low Voltage
V_IH1
V_IL1
V_OH1
V_OL1
V_OH2
V_OL2
1.3
–0.3
1.4
-
1.6
-
Max
V_DD+0.3
0.5
-
0.4
-
0.2
Units
V
V
V
V
V
V
Notes
|I_OH1|=2mA
I_OL1=2mA
|I_OH2|=100uA
I_OL2=100uA
Integrated Silicon Solution, Inc.- www.issi.com
25
Rev. B
10/02/2014