IS61WV51232ALL Datasheet, PDF (15/19 Pages) Integrated Silicon Solution, Inc – 512K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61WV51232ALL/ALS
IS61WV51232BLL/BLS
IS64WV51232BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 4 (Byte Controlled, Back-to-Back Write) ^(1,3)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
OE
CE _LOW
t SA
WE
BWa-d
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1. The internalWritetimeisdefinedbytheoverlapofandWE=LOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,butanycanbedeassertedtoterminate
the Write. The tSA, tHA, tSD, and tHD timing is referenced to the rising or falling edge of the signal that terminates the Write.
2. TestedwithOEHIGHforaminimumof4nsbeforeWE=LOWtoplacetheI/OinaHIGH-Zstate.
3. WEmaybeheldLOWacrossmanyaddresscyclesandtheBWa-dpinscanbeusedtocontroltheWritefunction.
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. 00B
04/23/08