IS61WV51216ALL Datasheet, PDF (12/20 Pages) Integrated Silicon Solution, Inc – 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWB
tPWE1
tPWE2
tSD
tHD
tHZWE⁽²⁾
tLZWE⁽²⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8
Min. Max.
8
—
6.5 —
6.5 —
0
—
0
—
6.5 —
6.5 —
8.0 —
5
—
0
—
— 3.5
2
—
-10
Min. Max.
Unit
10
—
ns
8
—
ns
8
—
ns
0
—
ns
0
—
ns
8
—
ns
8
—
ns
10
—
ns
6
—
ns
0
—
ns
—
5
ns
2
—
ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0Vandoutputloading
specified in Figure 1.
2. TestedwiththeloadinFigure2. Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandUBorLB,andWELOW. AllsignalsmustbeinvalidstatestoinitiateaWrite,but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write. Shaded area product in development
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09