IS61WV51216ALL Datasheet, PDF (10/20 Pages) Integrated Silicon Solution, Inc – 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-20 ns
Min. Max.
Unit
tRC
Read Cycle Time
20
—
ns
tAA
Address Access Time
— 20
ns
tOHA
Output Hold Time
2.5 —
ns
tACE
CE Access Time
— 20
ns
tDOE
OE Access Time
—
8
ns
tHZOE⁽²⁾
OE to High-Z Output
0
8
ns
tLZOE⁽²⁾
OE to Low-Z Output
0
—
ns
tHZCE⁽²
CE to High-Z Output
0
8
ns
tLZCE⁽²⁾
CE to Low-Z Output
3
—
ns
tBA
LB, UB Access Time
—
8
ns
tHZB
LB, UB to High-Z Output
0
8
ns
tLZB
LB, UB to Low-Z Output
0
—
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
10/01/09