ISL6549 Datasheet, PDF (9/18 Pages) Intersil Corporation – Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller

ISL6549
soft-start cycles (1 internal soft-start ramp cycle, plus
one-quarter on the next).
If either V_INx voltage is not present at startup, that will cause a
UV shutdown and restart cycle; similarly, if either V_INx is
removed after start-up, a shutdown and restart cycle will start
when its output drifts down to the UV trip point. But in both
cases, once the V_INx is restored, the V_OUTs will recover on
the next soft-start ramp.
1.6ms
6.4ms
V_OUT2 (0.5V/DIV)
dependence between the resistor chosen and the resulting
switching frequency.
Output Voltage Selection
The output voltage of the PWM converter can be programmed
to any level between V_IN1 and the internal reference, 0.8V.
However, even though the ISL6549 can run at near 100%
duty cycle at zero load, additional voltage margin is required
above V_IN1 to allow for loading. An external resistor divider is
used to scale the output voltage relative to the reference
voltage and feed it back to the inverting input of the error
amplifier (see Figure 7). A typical value for R1 may be 1.00kΩ
(±1% for accuracy), and then R4 (also ±1%) is chosen
according to Equation 1:
R4 = -------R-----1-----^×----0----.-8----V---------
VOUT1 – 0.8V
(EQ. 1)
V_OUT2 (0.5V/DIV)
GND>
V_OUT1 (0.5V/DIV)
FIGURE 5. UNDERVOLTAGE PROTECTION (SIMULATED BY
HAVING NO VIN1 ON POWER-UP)
Figure 5 shows an example of the start-up, with V_IN1 not
powered. V_OUT2 ramps up one-quarter of the way, at which
time the UV comparators are enabled. Since V_IN1 is not
present, V_OUT1 will not be following the soft-start ramp up,
and it will fail the test for UV, shutting down both outputs. It
starts an internal delay time-out (equal to one soft-start
interval), and then starts a new ramp. For this example, it
shows about a 1.6ms ramp up, and 6.4ms off, before the next
ramp starts. Thus, the total period of 8ms is based on 1.25
soft-start cycles (one-quarter of the first ramp, and then one
full time-out, at a clock period of around 1.6µs) The dotted
magenta line shows the case where V_OUT2 is allowed to
ramp all of the way up to 2V.
Switching Frequency
1M
100k
10k
100k
1M
R (kΩ)
FIGURE 6. FREQUENCY vs FS RESISTOR
The switching frequency of the ISL6549 is determined by the
value of the FS resistor. The graph in Figure 6 shows the
R1 is also part of the compensation circuit (see “PWM
Controller Feedback Compensation” on page 10 for more
details), so once chosen for that, it should not be changed to
adjust V_OUT1; only change R4. If the output voltage desired
is 0.8V, simply route V_OUT1 back to the FB pin through R1,
but do not populate R4. V_OUT1 voltages less than the 0.8V
reference are not available.
V_IN1
V_OUT1
C_IN1 ⁺
L_OUT
Q1
ISL6549
UGATE
PHASE
C_OUT1 ⁺
Q2
LGATE
R1
C2
R3
C3
FB
COMP
R2 C1
R4
VOUT₁ = 0.8 × _⎝⎛1 + ^RR-----14--_⎠⎞
FIGURE 7. OUTPUT VOLTAGE SELECTION OF THE
SWITCHER (V_OUT1)
The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 8. Select a
value for R5 (typical 1.00kΩ ±1% for accuracy), and use
Equation 2 to calculate R6 (also ±1%), where V_OUT2 is the
desired linear regulator output voltage and V_REF is the
internal reference voltage, 0.8V. For an output voltage of
0.8V, simply populate R5 with a value less than 5kΩ and do
not populate R6. V_OUT2 voltages less than the 0.8V
reference are not available.
R6 = -------R----⁵-----^×-----0---.--8----V--------
VOUT₂ – 0.8V
(EQ. 2)
9
FN9168.2
September 22, 2006