ISL6549 Datasheet, PDF (10/18 Pages) Intersil Corporation – Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller

ISL6549
For most situations, no external compensation is required for
the linear output. See “Linear Controller Feedback
Compensation” on page 12.
For both outputs, the selection of 1% resistors may not be
able to get the exact ratio desired for any given output voltage.
If the output must be defined better, then one option is to
place a much bigger resistor in parallel with R4 or R6, to lower
its value. For example, a 100kΩ in parallel with a 1.00kΩ
yields 990Ω, 1% below 1.00kΩ, which gives finer resolution
than the next lower size (976Ω 1%). The big resistor may not
have to be 1% tolerance either.
If the linear output is not required, connect the LDO_DR pin
directly to LDO_FB pin with no other components. This will
terminate the signals and keep the linear from tripping its
undervoltage, which would force both outputs into retry.
V_IN2
+
C_IN2
Q3
LDO_DR
V_OUT2
+
C_OUT2
R5
R6
LDO_FB
ISL6549
VOUT₂
=
0.8
×
⎛
⎝
1
+
RR-----56_{--⎠⎞}
FIGURE 8. OUTPUT VOLTAGE SELECTION OF THE LINEAR
(V_OUT2)
Converter Shutdown
Pulling and holding the FS_DIS pin near GND will shut down
both regulators; almost any NFET or other pull-down device
(<1kΩ impedance) should work. Upon release of the FS_DIS
pin, the regulators enter into a soft-start cycle which brings
both outputs back into regulation. The FS_DIS pin requires a
quiet GND to minimize jitter. To accomplish this, the FS
resistor and any pull-down device should be placed as close
as possible to the pin, and the GND should be kept away from
the noisy FET GND.
Boot Capacitor, Boot Refresh
A capacitor from the PHASE pin to the BOOT pin is required
for the bootstrap circuit for the Upper Gate. The V_IN1 voltage
(and thus the PHASE node) is allowed to go as high as a
nominal 12V (±10%) supply. A diode is included on the IC
(anode to PVCC5 pin, cathode to BOOT pin), such that the
PVCC5 (nominally around 5.25V) will be the bootstrap supply.
In the event that the UGATE is on for an extended period of
time, the charge on the boot capacitor can start to sag, raising
the R_DS(ON) of the upper FET. The ISL6549 has a circuit that
detects a long UGATE on-time (32 oscillator clock periods),
and forces the LGATE to go high for one oscillator cycle,
which allows the bootstrap capacitor time to recharge.
PWM Controller Feedback Compensation
This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
C2
R2 ^C1
COMP
FB
C3
R1
R3
ISL6549
V_DIFF (V_OUT)
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6549
CIRCUIT
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6549 circuit. The output voltage (V_OUT) is regulated to the
reference voltage, VREF. The error amplifier output (COMP pin
voltage) is compared with the oscillator (OSC) modified
saw-tooth wave to provide a pulse-width modulated wave with
an amplitude of V_IN at the PHASE node. The PWM wave is
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC
gain, given by d_MAXV_IN/V_OSC, and shaped by the output
filter, with a double pole break frequency at F_LC and a zero at
F_CE. For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represents
the total output capacitance and its equivalent series
resistance.
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE=
-----------¹------------
2π ⋅ C ⋅ E
(EQ. 3)
The compensation network consists of the error amplifier
(internal to the ISL6549) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate phase
margin (better than 45 degrees). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10.
10
FN9168.2
September 22, 2006