ISL6549 Datasheet, PDF (13/18 Pages) Intersil Corporation – Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller

ISL6549
transient. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance
(ESL) of these capacitors increases with case size and can
reduce the usefulness of the capacitor to high slew-rate
transient loading. Unfortunately, ESL is not always a
specified parameter. Work with your capacitor supplier and
measure the capacitor’s impedance with frequency to
select a suitable component. In most cases, multiple
electrolytic capacitors of small case size perform better
than a single large case capacitor.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of upper FET Q1 and the source of
lower FET Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum input
voltage and a voltage rating of 1.5 times is a conservative
guideline. The RMS current rating requirement for the input
capacitor of a buck regulator is approximately half the DC load
current. Several electrolytic capacitors may be needed.
Bootstrap Capacitor Selection
The boot diode is internal to the ISL6549, and uses PVCC5 to
charge the external boot capacitor. The size of the bootstrap
capacitor can be chosen by using the equations in Equation
12.
C_BO
O
T
≥
-^Q----^G-----^A----^T---^E--
∆V
and
where
Q_GATE
=
N_------•_-----Q_-----G-----•_----V_-----I-N---
V_GS
N is the number of upper FETs
Q_G is the total gate charge per upper FET
V_IN is the input voltage
V_GS is the gate-source voltage (~5V for ISL6549)
∆V is the change in boot voltage before and immediately
after the transfer of charge; typically 0.7V to 1.0V
C_BOOT ≥ -^Q----^G--_∆---^A-_V---^T---^E-- = ^N-----_V-^•---_G--^Q---_S--^G---_•--^•--_∆--^V--_V---^I-^N---= ¹-----^•-₅----³-_•--³--₀---^•_.--₇--¹---²-- = 0.113µF
(EQ. 12)
The last equation plugs in some typical values: N = 1;
Q_G is 33nC, V_IN is 12V, V_GS is 11V, ∆V_max = 1V. In this
example, C_BOOT ≥ 0.113µF. This value is often rounded to
0.1µF or 0.22µF as a starting value. The bootstrap capacitors
for the ISL6549 can usually be rated for 6.3V.
Switcher FET Considerations
The IC was designed for nominal 12V supply for V_IN1 (drain of
upper FET Q1). However, it will work with most any voltage
(from other supplies or other regulator outputs) down to
around 1V, as long as the input is above the output by a
sufficient margin (based on practical duty cycle limitations and
upper FET R_DS(ON) constraints). For example, although the
IC can function at near 100% duty cycle, the voltage drop due
to the R_DS(ON) of the upper FET at full load current will limit
the practical duty cycle to something less than 100%. So the
V_IN1 range is roughly 1.0V up to 12V, with the V_OUT1 range
slightly below it. Therefore, the FETs need to be rated for
drain-source breakdown above the V_IN1 voltage; 20V and
30V ratings are common.
The ISL6549 gate drivers (UGATE and LGATE) were
designed to drive up to 2 upper and 2 lower 8 Ld SOIC FETs;
when the FETs are properly sized, the output currents can
range from under 1A to over 20A. Driving more or bigger FETs
is not recommended; even if there is enough current (from the
internal PVCC5 regulator), the gate driver waveforms may be
degraded. DPAK FET packages can be used, but D²PAK
FETs are not recommended, due to the higher inductance of
the package leads. For example, the inductance in the source
of the lower FET can create large negative spikes on the
PHASE node when the UGATE turns off.
Both the UGATE and LGATE voltages are derived from the
internal PVCC5 internal regulator, typically 5.25V. UGATE is
only about 5.0V above PHASE, due to the drop in the internal
BOOT diode charging the BOOT capacitor; LGATE sees the
full 5.25V. So both are considered “5V” drivers; this affects the
FET selection in two ways. First, the FET gate-source voltage
rating can be as low as 12V (this rating is usually consistent
with the 20V or 30V breakdown chosen above). Second, the
FETs must have a low threshold voltage (around 1V), in order
to have its R_DS(ON) rating at V_GS = 4.5V in the 10mΩ-20mΩ
range. While some FETs are also rated with gate voltages as
low as 2.7V, with typical thresholds under 1V, these can cause
application problems. As LGATE shuts off the lower FET, it
does not take much ringing in the LGATE signal to turn the
lower FET back on, while the Upper FET is also turning on,
causing some shoot-through current. So avoid FETs with
thresholds below 1V.
Another set of important parameters are the turn-on and
turn-off times (internal propagation delays, how long before
the output starts to switch) and the rise and fall times (external
delay to complete the switching). The UGATE and LGATE
drivers use an adaptive technique to determine the dead time
(when both gate drivers signals are low). Comparators sense
when each driver is getting close to GND (such that its FET is
close to being off), before turning on the other. This technique
minimizes the dead time to the 10ns-20ns range. So if either
13
FN9168.2
September 22, 2006