ISL6549 Datasheet, PDF(8/18 Page) Intersil Corporation – Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller

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ISL6549 Datasheet, PDF (8/18 Pages) Intersil Corporation – Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller

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ISL6549

VOUT1

VOUT2

GND>

FIGURE 2. EXPANDED VIEW: VOLTAGE RAMP AND TIME

Undervoltage Protection

The FB and LDO_FB pins are each monitored during

converter operation by their own Undervoltage (UV)

comparator. If either FB voltage drops below 75% of the

reference voltage (75% of 0.8V = 0.6V), a fault signal is

internally generated, and the fault logic shuts down BOTH

regulators. The UV comparators are enabled when the

soft-start ramp is about one-quarter (25%) done.

(0.5V/DIV)

VOUT2 (2.5V)

VOUT1 (1.5V)

A few clock cycles are used for initialization to insure that soft-

start begins near zero volts. The ramps are the same, whether

triggered by releasing FS_DIS or by exceeding the POR trip

levels.

Both outputs use the same soft-start ramp, and the ramp time

is determined by the switching frequency. Thus, there is no

simple way to disable or sequence them independently, or to

change the ramp rate independently of the clock.

If the switcher output is already pre-charged to a voltage when

the regulator starts up, the ISL6549 will detect this condition

(see Figure 3). The red trace shows the normal ramp, when

the output starts at GND. The green trace shows the case

when the output is pre-charged to a voltage less than the final

output. The upper or lower FET does not turn on until the soft-

start ramp voltage exceeds the output; then the output starts

ramping seamlessly from there. If the output voltage is pre-

charged above the normal output level, as shown in the

magenta trace, neither FET will turn on until the end of the

soft-start ramp; then the output will be quickly pulled down to

the final value.

VCC12 > 9.5V

VCC12 (2V/DIV)

VOUT2 OVER-CHARGED (1V/DIV)

VOUT2 PRE-CHARGED (1V/DIV)

GND>

VOUT2 NO CHARGE (1V/DIV)

FIGURE 3. PRE-CHARGED OUTPUT

GND>

DELAY INTERVAL

INTERNAL SOFT-START FUNCTION

GND>

SOFT-START

DELAY

SOFT-START

DELAY

T1 T2

(T1 TO T2 NOT TO SCALE) TIME

FIGURE 4. UNDERVOLTAGE PROTECTION RESPONSE

Figure 4 illustrates the protection feature responding to a UV

event on VOUT1. At time T0, VOUT1 has dropped below 75%

of the nominal output voltage. Both outputs are quickly shut

down and the UGATE and LGATE stop switching immediately,

but the fall time of each output is determined by the load

and/or short condition on each plus the output capacitance

that needs to be discharged. The soft-start function begins

producing an internal soft-start ramp. The delay interval, T0 to

T1, seen by the output is equivalent to one soft-start cycle.

Then a normal soft-start ramp of the output starts, at time T1.

At the one-quarter point of the soft-start ramp (not drawn

exactly to scale), the good output will have ramped one-

quarter way up, while the shorted output will presumably be

lower than a quarter (depending on the magnitude of the

short). Once the UV comparators are enabled (at the

one-quarter point) both outputs will again shut down (if the

fault is still present on one of them). Time T2 starts a new

internal soft-start cycle, and at T3, starts a new ramp, similar

to T1. This time, if we assume the short has gone away, the

outputs will ramp up to T4 as they should. If the short has not

gone away, then the T0, T1, T2 hiccup mode cycle will keep

repeating indefinitely; this cycle time is the equivalent of 1.25

FN9168.2

September 22, 2006

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