ISL6549 Datasheet, PDF (11/18 Pages) Intersil Corporation – Single 12V Input Supply Dual Regulator Synchronous Rectified Buck PWM and Linear Power Controller

ISL6549
C2
COMP
R2 _C1
-
FB
E/A ⁺
VREF
R3 ^C3
R1
Ro
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_IN
L
UGATE
PHASE
LGATE
V_OUT
D
C
E
ISL6549 EXTERNAL CIRCUIT
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Use the following guidelines for locating the poles and zeros of
the compensation network:
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F₀). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 10, the design procedure can
be followed as presented.
R2 = ---^V----^O-----^S----^C-----^â‹---^R-----¹-----^â‹---^F----⁰----
d_MAX ⋅ V_IN ⋅ F_LC
(EQ. 4)
2. Calculate C1 such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C1 = -----------------------¹------------------------
2π ⋅ R2 ⋅ 0.5 ⋅ F_LC
(EQ. 5)
3. Calculate C2 such that F_P1 is placed at F_CE.
C2 = -₂---_π-----_â‹---_R-----₂-----_â‹---_CC-----₁₁----_â‹---_F----_C----_E-----–-----₁--
(EQ. 6)
4. Calculate R3 such that F_Z2 is placed at F_LC. Calculate C3
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of F_P2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R3 = --------^R----¹---------
-^F---^S----^W---- – 1
F_LC
C3 = ------------------------¹-------------------------
2π ⋅ R3 ⋅ 0.7 ⋅ F_SW
(EQ. 7)
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. Equation 8 describes the frequency
response of the modulator (G_MOD), feedback compensation
(G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
--------------------------¹-----+-----^s----⁽--^f--⁾----^â‹---^E-----^â‹---^C-----------------------------
1 + s(f) ⋅ (E + D) ⋅ C + s²(f) ⋅ L ⋅ C
G_FB(f) = _s----₍-¹-_f---₎-+--_â‹---_Rs----⁽-₁-^f--⁾--_â‹--^â‹-₍--^RC----²-₁----^â‹-+--^C---_C--¹--₂-----₎ ⋅
⋅ -------------------------------¹-----+-----^s---⁽--^f---⁾---^â‹---⁽---^R----¹-----+-----^R-----³----⁾---^â‹---^C-----³--------------------------------
(
1
+
s
(f)
⋅
R3
⋅
C
3)
⋅
⎝⎛ ¹
+
s(f)
⋅
R
2
⋅
⎛
⎝
C^-C----1^{-1----+-⋅---C-}C^----2-2^{--⎠⎞ ⎠⎞}
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
(EQ. 8)
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
---------------¹----------------
2π ⋅ R2 ⋅ C1
F_Z2
=
-------------------------¹--------------------------
2π ⋅ (R1 + R3) ⋅ C3
F_P1 = ₂----_π-----_â‹---_R-----₂-----_⋹---_{C--C--------1--1--------+-â‹}------_C--_C--------₂--₂----
F_P2
=
---------------¹----------------
2π ⋅ R3 ⋅ C3
(EQ. 9)
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the
log-log graph of Figure 11 by adding the modulator gain, G_MOD
(in dB), to the feedback compensation gain, G_FB (in dB). This is
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
11
FN9168.2
September 22, 2006