ISL23318_14 Datasheet, PDF (9/19 Pages) Intersil Corporation – Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23318
Timing Diagrams
SDA vs SCL Timing
t_F
t_HIGH
t_LOW
SCL
t_SU:STA
SDA
(INPUT TIMING)
t_SU:DAT
t_HD:STA
t_HD:DAT
SDA
(OUTPUT TIMING)
t_R
t_sp
t_AA t_DH
t_SU:STO
t_BUF
A0 and A1 Pin Timing
SCL
START
CLK 1
STOP
SDA
A0, A1
t_SU:A
t_HD:A
Typical Performance Curves
0.4
0.2
0
-0.2
-0.4
0
16
32
48
64
80
96 112 128
TAP POSITION (DECIMAL)
FIGURE 3. 10k DNL vs TAP POSITION, V_CC = 5V
0.04
0.02
0
-0.02
-0.04
0
16
32
48
64
80
96 112 128
TAP POSITION (DECIMAL)
FIGURE 4. 50k DNL vs TAP POSITION, V_CC = 5V
9
FN7887.0
July 26, 2011