ISL23318_14 Datasheet, PDF (14/19 Pages) Intersil Corporation – Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23318
monotonically from the position closest to RL to the position
closest to RH. At the same time, the resistance between RW
and RL increases monotonically, while the resistance between
RH and RW decreases monotonically.
While the ISL23318 is being powered up, the WR is reset to 40h
(64 decimal), which locates RW roughly at the center between R_L
and R_H.
The WR can be read or written to directly using the I²C serial
interface as described in the following sections.
Memory Description
The ISL23318 contains two volatile 8-bit registers: Wiper Register
(WR) and Access Control Register (ACR). The memory map of
ISL23318 is shown in Table 1. The Wiper Register (WR) at address 0
contains current wiper position. The Access Control Register (ACR)
at address 10h contains information and control bits described
in Table 2.
ADDRESS
(hex)
10
0
TABLE 1. MEMORY MAP
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
ACR
40
WR
40
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME/ 0 SHDN 0 0
0
0
0
0
VALUE
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor as shown in Figure 25. Default value of the
SHDN bit is 1
RH
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
In the shutdown mode, the RW terminal is shorted to the RL
terminal with around 2kΩ resistance as shown in Figure 25. When
the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
POWER-UP
MID SCALE = 80H
USER PROGRAMMED
AFTER SHDN
SHDN ACTIVATED ^{SHDN RELEASED}
WIPER RESTORE TO
THE ORIGINAL POSITION
SHDN MODE
0
TIME (s)
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
I²C Serial Interface
The ISL23318 supports an I²C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23318 operates as a slave device
in all applications.
All communication over the I²C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23318, the SDA pin is in the input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL23318 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
The ISL23318 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
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FN7887.0
July 26, 2011