ISL23318_14 Datasheet, PDF (13/19 Pages) Intersil Corporation – Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23318
Typical Performance Curves (Continued)
CH1: 0.5V/DIV, 0.2µs/DIV RH PIN
1.2
CH2: 0.2V/DIV, 0.2µs/DIV RW PIN
1.0
0.8
0.6
V_CC = 5.5V, V_LOGIC = 5.5V
0.4
V_CC = 1.7V, V_LOGIC = 1.2V
0.2
R_TOTAL = 10k
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
0
-40
-15
10
35
60
85
110
TEMPERATURE (°C)
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Functional Pin Descriptions
Potentiometers Pins
RH AND RL
The high (R_H) and low (R_L) terminals of the ISL23318 are
equivalent to the fixed terminals of a mechanical potentiometer.
R_H and R_L are referenced to the relative position of the wiper and
not the voltage potential on the terminals. With WR set to 127
decimal, the wiper will be closest to R_H, and with the WR set to 0,
the wiper is closest to R_L.
RW
RW is the wiper terminal, and it is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for I²C
interface. It receives device address, wiper address and data
from an I²C external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of the
serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I²C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits of
the 7-bit I²C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23318. A
maximum of four ISL23318 devices may occupy the I²C serial
bus (see Table 3).
V_LOGIC
This is an input pin that supplies internal level translator for serial
bus operation from 1.2V to 5.5V.
Principles of Operation
The ISL23318 is an integrated circuit incorporating one DCP with
its associated registers and an I²C serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
Voltage at any DCP pins, R_H, R_L or R_W, should not exceed V_CC
level at any conditions during power-up and normal operation.
The V_LOGIC pin needs to be connected to the I²C bus supply
which allows reliable communication with the wide range of
microcontrollers and independent of the V_CC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the wiper
terminal of a mechanical potentiometer. The position of the
wiper terminal within the DCP is controlled by a 7-bit volatile
Wiper Register (WR). When the WR of a DCP contains all zeroes
(WR[7:0] = 00h), its wiper terminal (RW) is closest to its “Low”
terminal (RL). When the WR register of a DCP contains all ones
(WR[7:0] = 7Fh), its wiper terminal (RW) is closest to its “High”
terminal (RH). As the value of the WR increases from all zeroes
(0) to 0111 1111b (127 decimal), the wiper moves
13
FN7887.0
July 26, 2011