ISL23318_14 Datasheet, PDF (15/19 Pages) Intersil Corporation – Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23318
after successful receipt of an Address Byte. The ISL23318 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 10100 as the five MSBs, and
the following two bits matching the logic values present at pins
A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
1
0
1
0
0
A1 A0 R/W
(MSB)
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
STOP
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM
THE MASTER
WRITE
S
T
A _{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
1 0 1 0 0 A1 A0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 29. BYTE WRITE SEQUENCE
15
FN7887.0
July 26, 2011