ISL23318_14 Datasheet, PDF (7/19 Pages) Intersil Corporation – Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23318
Serial Interface Specification For SCL, SDA, A0, A1 unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
V_IL
V_IH
Hysteresis
V_OL
C_pin
f_SCL
t_sp
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
V_LOGIC > 2V
V_LOGIC < 2V
I_OL = 3mA, V_LOGIC > 2V
I_OL = 1.5mA, V_LOGIC < 2V
Any pulse narrower than the
max spec is suppressed
-0.3
0.7 x V_LOGIC
0.05 x V_LOGIC
0.1 x V_LOGIC
0
t_AA
SCL Falling Edge to SDA Output SCL falling edge crossing 30%
Data Valid
of V_LOGIC, until SDA exits the
30% to 70% of V_LOGIC window
t_BUF
Time the Bus Must be Free Before SDA crossing 70% of V_LOGIC
the Start of a New Transmission during a STOP condition, to
SDA crossing 70% of V_LOGIC
during the following START
condition
1300
t_LOW
Clock LOW Time
t_HIGH
Clock HIGH Time
t_SU:STA
START Condition Set-up Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Set-up Time
t_HD:DAT Input Data Hold Time
Measured at the 30% of
V_LOGIC crossing
Measured at the 70% of
V_LOGIC crossing
SCL rising edge to SDA falling
edge; both crossing 70% of
V_LOGIC
From SDA falling edge
crossing 30% of V_LOGIC to SCL
falling edge crossing 70% of
V_LOGIC
From SDA exiting the 30% to
70% of V_LOGIC window, to SCL
rising edge crossing 30% of
V_LOGIC
From SCL falling edge crossing
70% of V_CC to SDA entering
the 30% to 70% of V_LOGIC
window
1300
600
600
600
100
0
t_SU:STO
t_HD:STO
t_DH
t_R
STOP Condition Set-up Time
From SCL rising edge crossing
600
70% of V_LOGIC, to SDA rising
edge crossing 30% of V_LOGIC
STOP Condition Hold Time for Read From SDA rising edge to SCL
or Write
falling edge; both crossing
70% of V_LOGIC
1300
Output Data Hold Time
From SCL falling edge crossing
0
30% of V_LOGIC, until SDA
enters the 30% to 70% of
V_LOGIC window.
I_OL = 3mA, V_LOGIC > 2V.
I_OL = 0.5mA, V_LOGIC < 2V
SDA and SCL Rise Time
From 30% to 70% of V_LOGIC 20 + 0.1 x Cb
TYP
(Note 8)
10
MAX
(Note 20)
0.3 x V_LOGIC
V_LOGIC + 0.3
0.4
0.2 x V_LOGIC
400
50
900
250
UNITS
V
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
FN7887.0
July 26, 2011