X4043-45 Datasheet, PDF (8/24 Pages) Intersil Corporation – 2.7V to 5.5V power supply operation

X4043, X4045
Figure 5. V_TRIP Programming Sequence
V_TRIP Programming
No
Desired
V_TRIP <
Present Value ?
YES
Execute
V_TRIP Reset Sequence
New V_CC applied =
Old V_CC applied + | Error |
Set V_CC = desired V_TRIP
Execute
Set Higher V_TRIP Sequence
Power-down
the Device
Let: MDE = Maximum Desired Error
MDE⁺
Desired Value
MDE^–
Acceptable
Error Range
Error = Actual – Desired
New V_CC applied =
Old V_CC applied – | Error |
Execute Reset V_TRIP
Sequence
NO
Error < MDE^–
Ramp V_CC
Output Switches?
(RESET)
YES
Actual V_TRIP –
Desired ^VTRIP
= Error
| Error | < | MDE |
Error > MDE⁺
DONE
Control Register
The control register provides the user a mechanism for
changing the block lock and watchdog timer settings.
The block lock and watchdog timer bits are nonvolatile
and do not change when power is removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte
write operation directly to the address of the register
and only one data byte is allowed for each register
write operation. Prior to writing to the control register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register".
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4043/45 will
not acknowledge any data bytes written after the first
byte is entered.
8
FN8118.3
December 9, 2015