X4043-45 Datasheet, PDF (4/24 Pages) Intersil Corporation – 2.7V to 5.5V power supply operation

X4043, X4045
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on an I²C bus.
The device utilizes Intersil’s proprietary Direct Write^™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
8-Pin JEDEC SOIC, MSOP
(PDIP no longer available or supported)
NC ¹
NC 2
RESET ³
V_SS 4
8 V_CC
7 _WP
6 SCL
5 SDA
Pin
(SOIC/MSOP/DIP)
1
2
3
4
5
6
7
8
Name
NC
NC
RESET/RESET
V_SS
SDA
SCL
WP
V_CC
Function
No internal connections
No internal connections
Reset Output. RESET is an active LOW, open drain output which goes active
whenever V_CC falls below V_TRIP. It will remain active until V_CC rises above the
V_TRIP for t_PURST. RESET/RESET goes active if the Watchdog Timer is enabled
and SDA remains either HIGH or LOW longer than the selectable Watchdog time
out period. RESET/RESET goes active on power-uppower-up and remains
active for 250ms after the power supply stabilizes. RESET is an active high open
drain output. An external pull up resistor is required on the RESET/RESET pin.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Serial Clock. The Serial Clock input controls the serial bus timing for data input and
output.
Write Protect. WP HIGH prevents writes to any location in the device (including
the control register). Connect WP pin to V_SS when it is not used.
Supply Voltage
4
FN8118.3
December 9, 2015