X4043-45 Datasheet, PDF (12/24 Pages) Intersil Corporation – 2.7V to 5.5V power supply operation

X4043, X4045
Figure 10. Byte Write Sequence
S
Signals from
the Master
t
a
r
Slave
Address
t
SDA Bus
0
Byte
Address
S
t
Data
o
p
Signals from
the Slave
A
A
A
C
C
C
K
K
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 16 bytes to the page starting at
any location on that page. If the master begins writing
at location 10, and loads 12 bytes, then the first 5
bytes are written to locations 10 through 15, and the
last 7 bytes are written to locations 0 through 6. After-
wards, the address counter would point to location 7 of
the page that was just written. If the master supplies
more than 16 bytes of data, then new data over-writes
the previous data, one byte at a time.
Figure 11. Page Write Operation
S
Signals from
the Master
t
a
r
Slave
Address
t
Byte
Address
(1  n 16)
Data
(1)
Data
(n)
S
t
o
p
SDA Bus
0
Signals from
the Slave
A
A
A
A
C
C
C
C
K
K
K
K
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10
7 Bytes
Address
=6
Address Pointer
Ends Here
Addr = 7
The master terminates the data byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the inter-
nal write cycle. See Figure 11 for the address,
acknowledge, and data transfer sequence.
5 Bytes
Address
10
Address
n-1
Stops and Write Modes
Stop conditions (that terminate write operations) must
be sent by the master after sending at least 1 full data
byte, plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full data
byte plus its associated ACK is sent, then the device
will reset itself without performing the write. The con-
tents of the array will not be effected.
12
FN8118.3
December 9, 2015