X4043-45 Datasheet, PDF (5/24 Pages) Intersil Corporation – 2.7V to 5.5V power supply operation

X4043, X4045
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4043/45 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
When V_CC exceeds the device V_TRIP threshold value
for 200ms (nominal) the circuit releases
RESET/RESET allowing the system to begin operation.
Low Voltage Monitoring
During operation, the X4043/45 monitors the V_CC level
and asserts RESET/RESET if supply voltage falls
below a preset minimum V_TRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V_CC returns and exceeds
V_TRIP for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two
nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
Figure 1. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Start
WDT Reset Stop
EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V_CC < V_TRIP), any in-progress com-
munications are terminated. While V_CC < V_TRIP, no new
communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET/RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V_TRIP Programming
The X4043/45 is shipped with a standard V_CC thresh-
old (V_TRIP) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard V_TRIP is not exactly
right, or if higher precision is needed in the V_TRIP
value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a high voltage control signal.
Figure 2. Set V_TRIP Level Sequence (V_CC = desired V_TRIP values WEL bit set)
WP
V_P = 15-18V
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SCL
SDA
A0h
01h
00h
5
FN8118.3
December 9, 2015