X4043-45 Datasheet, PDF (15/24 Pages) Intersil Corporation – 2.7V to 5.5V power supply operation

X4043, X4045
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the control register to change watchdog timer or
block lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and the control register.
– Communication to the device is inhibited as a result
of a low voltage condition (V_CC < V_TRIP)any in-prog-
ress communication is terminated.
– Block lock bits can protect sections of the memory
array from write operations.
Symbol Table
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
15
FN8118.3
December 9, 2015