ISL6505 Datasheet, PDF (8/17 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

ISL6505
The internal circuitry does not allow the transition from an
S4/S5 (suspend to disk/soft off) state to an S3 (suspend to
RAM) state; however, it does allow the transition from S3 to
S4/S5. The only ‘legal’ transitions are from an active state
(S0, S1) to a sleep state (S3, S5) and vice versa.
TABLE 1. 5V_DUAL OUTPUT (V_OUT4) AND 3.3VDL/SB (V_OUT3)
TRUTH TABLE
S5 S3 3.3VDL/SB 5VDL
COMMENTS
1
1
3.3V
5V S0/S1/S2 States (Active)
1
0
3.3V
5V S3
0
1
Note
Maintains Previous State
0
0
3.3V
0V S4/S5 (EN5 = GND)
0
0
3.3V
5V S4/S5 (EN5 = open/5V)
NOTE: Combination Not Allowed.
TABLE 2. V_OUT1 AND 1V2VID (V_OUT2) TRUTH TABLE
S5 S3
1
1
V_OUT1
1.5V
1V2VID
COMMENTS
1.2V S0/S1/S2 States (Active)
1
0
0V
0V S3 (LAN = GND)
1
0
1.5V
0V S3 (LAN = open/5V)
0
1
Note
Maintains Previous State
0
0
0V
0V S4/S5 (LAN = GND)
0
0
1.5V
0V S4/S5 (LAN = open/5V)
NOTE: Combination Not Allowed.
Functional Timing Diagrams
Figures 4 (EN5 = low), 5 (EN5 = high), and 6 are timing
diagrams, detailing the power up/down sequences of all the
outputs in response to the status of the sleep-state pins (S3,
S5), as well as the status of the input ATX supply. Not shown in
these diagrams is the deglitching feature used to protect
against false sleep state tripping. Both S3 and S5 pins are
protected against noise by a 2µs filter (typically 1–4µs). This
feature is useful in noisy computer environments if the control
signals have to travel over significant distances. Additionally,
the S3 pin features a 200µs delay in transitioning to sleep
states. Once the S3 pin goes low, an internal timer is
activated. At the end of the 200µs interval, if the S5 pin is
low, the ISL6505 switches into S5 sleep state; if the S5 pin is
high, the ISL6505 goes into S3 sleep state.
The shaded column in Figures 4 and 5 highlights the
difference on the 5VDLSB and 5VDL pins for the two EN5
states.
5VSB
S3
S5
3.3V, 5V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 4. 5V_DUAL AND 3.3V_DUAL/3.3V_SB TIMING
DIAGRAM; EN5 = GND
5VSB
S3
S5
3.3V, 5V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 5. 5V_DUAL AND 3.3V_DUAL/3.3V_SB TIMING
DIAGRAM; EN5 = 5V/OPEN
5VSB
S3
S5
3.3V,
5V, 12V
DLA
V_OUT1
(LAN=5V)
1V2VID
V_OUT1 (LAN=GND)
FIGURE 6. V_OUT1 AND 1.2V_VID TIMING DIAGRAM (NOTE
THE DEPENDENCE OF V_OUT1 ON THE LOGIC
STATE OF LAN PIN)
8