ISL6505 Datasheet, PDF (7/17 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

ISL6505
SS (Pin 17 SOIC; Pin 14 QFN)
Connect this pin to a small ceramic capacitor (no less than
5nF; 0.1µF recommended). The internal soft-start (SS)
current source along with the external capacitor creates a
voltage ramp used to control the ramp-up of the output
voltages. Pulling this pin low (to GND) with an open-drain
device shuts down all the outputs as well as forces the
FAULT pin low. The C_SS capacitor is also used to provide a
controlled voltage slew rate during active-to-sleep transitions
on the 3.3V_DUAL/3.3V_SB output.
3V3DL (Pin 4 SOIC; Pin 1 QFN)
Connect this pin to the 3.3V dual/stand-by output (V_OUT3).
In sleep states, the voltage at this pin is regulated to 3.3V; in
active states, ATX 3.3V output is delivered to this node
through a fully-on NFET transistor. During all operating
states, this pin is monitored for undervoltage events. This pin
provides all the output current delivered by V_OUT1.
3V3DLSB (Pin 3 SOIC; Pin 20 QFN)
Connect this pin to the base of a suitable NPN transistor. In
sleep state, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 13 SOIC; Pin 10 QFN)
This pin is an open-collector output. Connect a 1kΩ resistor
from this pin to the ATX 12V output. This resistor is used to
pull the gates of suitable NFETs to 12V, which in active
state, switch in the ATX 3.3V and 5V outputs into the
3.3V_DUAL/3.3V_SB and 5V_DUAL outputs, respectively.
5VDL (Pin 15 SOIC; Pin 12 QFN)
Connect this pin to the 5V_DUAL output (V_OUT4). In either
operating state (when on), the voltage at this pin is provided
through a fully-on MOSFET transistor. This pin is also
monitored for undervoltage events.
5VDLSB (Pin 14 SOIC; Pin 11 QFN)
Connect this pin to the gate of a suitable PFET or bipolar
PNP. This transistor is switched on, connecting the ATX
5V_SB output to the 5V_DUAL regulator output during S3, and
if EN5 is open or high, during S5. If EN5 is low (GND), the
transistor is switched off in S5.
DR1 (Pin 2 SOIC; Pin 19 QFN)
This output pin drives the gate of an external NFET
transistor to create V_OUT1, which draws its output current
from the 3V3DL pin.
FB1 (Pin 1 SOIC; Pin 18 QFN)
This analog input pin looks at the V_OUT1 external resistor
divider, and compares it to the internal reference (0.8V
nominal), in order to regulate the voltage on V_OUT1. This pin
is also monitored for undervoltage events.
1V2VID (Pin 5 SOIC; Pin 2 QFN)
This pin is the output of the internal 1.2V voltage identification
(VID) regulator (V_OUT2). This internal regulator operates only
7
in active states (S0, S1/S2) and is shut off during any sleep
state. This regulator draws its output current from the 3V3 pin.
This pin is monitored for undervoltage events.
VID_PG (Pin 18 SOIC; Pin 15 QFN)
This pin is the open collector output of the 1V2VID power
good comparator. Connect a 10kΩ pull-up resistor from this
pin to the 1V2VID output. As long as the 1V2VID output is
below its PG threshold (typically 90% of final value), this pin
is pulled low. Once the PG threshold is reached, the VID_CT
pin starts charging its capacitor (setting the delay); when it
reaches its trip point, then the VID-PG pin releases, and
goes high (through the external pull-up resistor).
VID_CT (Pin 19 SOIC; Pin 16 QFN)
Connect a small capacitor from this pin to ground. The
capacitor is used to delay the VID_PG reporting the 1V2VID
has reached power good limits.
Description
Operation
The ISL6505 controls 4 output voltages (Refer to Figures 1,
2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5V_SB, and 12V bias input from an
ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
V_OUT1 (1.2V - 1.5V programmable), 3.3V_SB and PCI slots’
3.3V_AUX power (V_OUT3), the 1.2V VID circuitry power
(V_OUT2), a dual switch controller supplying the 5V_DUAL
voltage (V_OUT4), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization and POR
The ISL6505 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V_SB input supply voltage, initiating
3.3V_DUAL/3.3V_SB and 1.5V_SB soft-start operation shortly
after exceeding POR threshold.
Note that while the 5VSB pin has the main POR, both the
3V3 and 5V pins (12V is not monitored) must rise above
their own POR levels (typically 90%) in order to transition
into the S0/S1 active state. If during normal operation either
one drops below their falling trip points, the IC will go to the
S5 sleep mode. When both are back above their rising
thresholds, the IC will again soft-start into active state.
Output Operational Truth Tables
Table 1 describes the truth combinations pertaining to the
3.3V_DUAL/SB and 5V_DUAL dual outputs. The last two lines
highlight the difference between EN5 connected high or low.
Table 2 describes the truth combinations pertaining to the
V_OUT1 (typically between 1.2V and 1.5V) and 1V2VID
outputs. The last two sets of lines highlight the difference
between the two LAN pin modes (5V/open is the 10/100 LAN
mode; GND is the Gigabit Ethernet mode).