ISL6505 Datasheet, PDF (14/17 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

ISL6505
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an ISL6505 application must have a
sufficiently low ESR so as not to allow the input voltage to
dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6505’s regulation levels could have as a
result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, such phenomena could be responsible for the
5V_SB voltage drooping excessively and affecting the output
regulation. The solution to such a potential problem is using
larger input capacitors with a lower total combined ESR.
Transistor Selection/Considerations
The ISL6505 usually requires one P-Channel (or bipolar
PNP), three N-Channel MOSFETs, and one bipolar NPN
transistors. Note there is no Q1 listed below.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat.
The power dissipated in a linear regulator or an ON/OFF
switching element is
P_LINEAR = I_O × (V_IN – V_OUT)
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q2
The NPN transistor used as sleep state pass element on the
3.3V_DUAL output has to have a minimum current gain of 100
at 1.5V V_CE and 650mA I_CE throughout the in-circuit
operating temperature range. For larger current ratings on
the 3.3V_DUAL output (providing the ATX 5V_SB output rating
is equally extended), selection criteria for Q2 include an
appropriate current gain (h_fe) and saturation characteristics.
Q3, Q5
These NMOS FETs are used to switch the 3.3V and 5V inputs
provided by the ATX supply into the 3.3V_DUAL/3.3V_SB and
5V_DUAL outputs while in active (S0, S1) state. The main
criteria for the selection of these transistors is output voltage
budgeting. The maximum r_DS(ON) allowed at highest junction
temperature can be expressed with the following equation:
r_DS(ON)max
=
V_{-----I--N----m-----i-n-----–----}V_{----O-----U----T----m----i--n- , where}
I_OUTmax
V_INmin - minimum input voltage
V_OUTmin - minimum output voltage allowed
I_OUTmax - maximum output current
Q4
If a PMOS FET is used to switch the 5V_SB output of the ATX
supply into the 5V_DUAL output during sleep states, then the
selection criteria of this device is proper voltage budgeting.
The maximum r_DS(ON), however, has to be achieved with
only 4.5V of gate-to-source voltage, so a logic level
MOSFET needs to be selected. If a PNP device is chosen to
perform this function, it has to have a low- saturation voltage
while providing the maximum sleep current and have a
current gain sufficiently high to be saturated using the
minimum drive current (typically 20mA).
Q6
This NMOS FET acts as the pass transistor for the V_OUT1
output. The input voltage to the source comes from
3.3V_DUAL/3.3V_SB; the output is expected to be in the 1.2V
to 1.5V range, depending upon the external resistor divider.
The power dissipation will (3.3V - VOUT1) * IOUT1, so the
FET selection and mounting technique must be sufficient for
that case.
In addition, Q6 must have a sufficiently low gate threshold
voltage. The DR1 gate driver maximum voltage is limited to
a V_BE below the 5V supply (5VSB pin), which itself can be
as low as 4.5V. So the maximum driver voltage can be 3.8V
(or even a few tenths of a volt lower, considering
temperature effects of the V_BE drop). If the output voltage is
1.5V, then only 2.3V is available for the gate threshold, plus
any overdrive needed to get the required output current out
while close to the threshold. So a FET gate threshold voltage
well below 2V is recommended.
Although the design intended to use a low threshold voltage
FET for Q6, it is possible to use an NPN. The DR1 driver is
rated at 10mA nominal, but the driver will only supply the
current that is needed, up to 50mA; in that sense, it is more
of a maximum spec. That means an NPN with a gain of 100
could deliver up to 1.0A, for example. The additional base
current will come from the 5VSB pin, which adds some IC
power dissipation, and may take away current needed
elsewhere; it may also draw the extra current during sleep
modes. But the NPN can be used, and it should be stable,
using the same considerations for a FET.
The LAN pin determines the timing and the on state of the
regulator; when LAN is high (5V) or open, V_OUT1 stays on all
of the time. The input current comes from 3.3V_DUAL/3.3V_SB,
which indirectly comes from 3V3 during active modes, and
from the 3.3V_SB regulator (which ultimately comes from
5V_SB); thus, the V_OUT1 current is limited in sleep mode to
whatever current the 5V_SB has left, after all other currents
are accounted for. The current in active mode can be higher,
limited mainly by the dissipation of the FET.
When the LAN pin is low, then V_OUT1 is on only during
active states, where the input voltage is ultimately 3V3. So
again, the current is limited mainly by the dissipation of the
FET.
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