ISL6505 Datasheet, PDF (6/17 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

Pinouts
ISL6505 (20 LEAD WIDE SOIC)
TOP VIEW
FB1 1
DR1 2
3V3DLSB 3
3V3DL 4
1V2VID 5
3V3 6
5V 7
EN5 8
S3 9
S5 10
20 5VSB
19 VID_CT
18 VID_PG
17 SS
16 LAN
15 5VDL
14 5VDLSB
13 DLA
12 FAULT
11 GND
ISL6505
ISL6505 (5X5 QFN)
TOP VIEW
20 19 18 17 16
3V3DL 1
1V2VID 2
3V3 3
5V 4
EN5 5
15 VID_PG
14 SS
13 LAN
12 5VDL
11 5VDLSB
6 7 8 9 10
NOTE: The QFN bottom pad is electrically connected to the IC
substrate, at GND potential. It can be left unconnected, or connected
to GND; do NOT connect to another potential.
Functional Pin Description (Pin numbers for SOIC and QFN)
3V3 (Pin 6 SOIC; Pin 3 QFN)
Connect this pin to the ATX 3.3V output. This pin provides
the output current for the 1V2VID pin, and is monitored for
power quality.
5V (Pin 7 SOIC; Pin 4 QFN)
Connect this pin to the ATX 5V output. This pin is only
monitored for power quality.
5VSB (Pin 20 SOIC; Pin 17 QFN)
Provide a very well de-coupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5V_SB output. This pin
provides all the chip’s bias as well as the base current for Q2
(see typical application diagram). The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 11 SOIC; Pin 8 QFN)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
S3 and S5 (Pins 9, 10 SOIC; Pins 6, 7 QFN)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 50µA (typical) current source pull-
ups to 5VSB. Internal circuitry de-glitches these pins for
disturbances lasting as long as 2µs (typically). Additional
circuitry blocks illegal state transitions (such as S4/S5 to S3),
but does allow S3 to S4/S5. Connect S3 and S5
respectively to the computer system’s SLP_S3 and SLP_S5
signals.
EN5 (Pin 8 SOIC; Pin 5 QFN)
This digital input selects whether the 5VDL output stays up
or shuts down during the S5 Sleep Mode. It has a 10µA
typical pull-up current source. A logic high (5V) or open will
keep the 5VDL on during S5; a logic low (GND) will shut it off
during S5. NOTE: This pin should be tied low or high (or
open) on the board; it was not designed to be changed
during normal operation.
LAN (Pin 16 SOIC; Pin 13 QFN)
This digital input selects between two modes for the V_OUT1
regulator. It has a 10µA pull-up current source. A logic high
(5V) or open selects the 10/100 LAN mode, where V_OUT1
stays on all of the time (active and sleep modes). A logic low
(GND) selects the Gigabit Ethernet mode, where V_OUT1 is
only on during active (S0, S1) modes. Note that this
selection is independent of the voltage selection of V_OUT1
(which is determined by the external resistor divider). NOTE:
This pin should be tied low or high (or open) on the board; it
was not designed to be changed during normal operation.
FAULT (Pin 12 SOIC; Pin 9 QFN)
This digital output pin is used to report the fault condition by
being pulled to 5VSB (pulled to GND if no fault). It is a
CMOS digital output; an external pull-down resistor is NOT
required. In case of an undervoltage on any of the controlled
outputs, on any of the monitored ATX voltages (3V3 or 5V;
not 12V), or in case of an overtemperature event, this pin is
used to report the fault condition.
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