ISL6505 Datasheet, PDF (13/17 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

ISL6505
Layout Considerations
The typical application employing an ISL6505 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the
controller IC should be placed first. The controller should
be placed in a central position on the motherboard, closer
to the memory controller chip and processor, but not
excessively far from the 3.3V_DUAL island or the I/O
circuitry. Ensure the 1V2VID, 3V3, and 3V3DL connections
are properly sized to carry 100mA without exhibiting
significant resistive losses at the load end. Similarly, the
input bias supply (5V_SB) can carry a significant level of
current - for best results, ensure it is connected to its
respective source through an adequately sized trace. The
pass transistors should be placed on pads capable of
heatsinking matching the device’s power dissipation.
Where applicable, multiple via connections to a large
internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the high-
frequency decoupling capacitors should be placed as close as
possible to the load they are decoupling; the ones decoupling
the controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
electrolytics or tantalum capacitors) placement is not as
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
The critical small signal components include the soft-start
capacitor, C_SS, as well as all the high-frequency decoupling
capacitors. Locate these components close to the respective
pins of the control IC, and connect them to ground through a
via placed close to the ground pad. Minimize any leakage
current paths from the SS node, as the internal current
source is only 10µA (typical).
A multi-layer printed circuit board is recommended.
Figure 12 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Ideally, the power
plane should support both the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers to create power islands connecting the filtering
components (output capacitors) and the loads. Use the
remaining printed circuit layers for small signal wiring.
+12V_IN
+5V_SB
C5VSB
CIN
C_HF1
CSS
C_BULK1
Q6
V_OUT1
5VSB
SS
5VDLSB
5VDL
ISL6505
DR1
C_BULK4
FB1
DLA
Q4
V_OUT4
C_HF4
Q5
Q2
3V3DLSB 5V
V_OUT3
C_BULK3 ^CHF3
3V3DL
1V2VID
3V3 GND
Q3
+5V_IN
C_BULK2
V_OUT2
C_HF2
+3.3V_IN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0, S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
Also, during the transition between active and sleep states
on the 3.3V_DUAL/3.3V_SB and 5V_DUAL outputs, there is a
short interval of time during which none of the power pass
elements are conducting - during this time the output
capacitors have to supply all the output current. The output
voltage drop during this brief period of time can be easily
approximated with the following formula:
∆V _{O U T}
=
I_OUT
×

E

S
R_OUT
+
C^-----_O^--t--t-_U^----_T^-_{}
, where
∆V_OUT - output voltage drop
ESR_OUT - output capacitor bank ESR
I_OUT - output current during transition
C_OUT - output capacitor bank capacitance
t_t - active-to-sleep or sleep-to-active transition time (10µs typ.)
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