ISL5217 Datasheet, PDF (8/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
Data Modulation Path
Three data path options are provided, one for each
modulation format. The modulation format is selected using
FIR Control (0xd, 3:2). The modulation paths are defined in
the following subsections.
WR
CLK
1234
DLY DATA
DFF 1
DFF 2
DFF 3
DFF 4
Write_FIFO
REG1
FIFO NEEDS
FIFORDY MORE DATA
FIFO NEEDS
MORE DATA
FIGURE 5. FIFO DATA AND ENABLE TIMING
SDA
SDB
SDC
SDD
A<6:0>
P<15:0>
A(000)
WR
CLOCK SYNCHRONIZATION
DFF1 DFF2 DFF3 DFF4
R
R
R
R
E
E
E
E
G
G
G
G
>>>>
0X11, 15
0X11, 1:0
0X11, 3:2
0X12, 9:0
0X13, 9:0
SERIAL_WRITE_TO_FIFO
0X11, 15
ZERO’S
A(2:0)
R
R
E
E
G
G
>>
0X0, 15:0
0X1, 15:0
I SAMPLE (15:0)
0XC, 10:8
ALMOST EMPTY
THRESHOLD
Q SAMPLE (15:0)
FM ENABLED
WRITE_FIFO
R
R
R
R
R
E
E
E
E
E
G
G
G
G
G
>>>>>
8:1 MUX
IFIFO(15:0)
8:1 MUX
FIFORDY
QFIFO(15:0)
† All Registers are clocked at CLK unless shown otherwise.
R
R
R
R
R
R
R
E
E
E
E
E
E
E
G
G
G
G
G
G
G
>>>>>>>
WRITE_FIFO
FIGURE 6. I AND Q FIFO BLOCK DIAGRAM
8