ISL5217 Datasheet, PDF (17/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
register and slave register pair for each configuration
parameter and I/Q sample. The slave register for the I/Q
samples is the first location of the FIFO. The master
registers are clocked by the µP write strobe, are writable and
cleared by a hard reset. The slave registers are clocked by
device clock, are readable and cleared by either a hard or
soft reset. The transfer of configuration data from the master
register to the slave register can occur synchronously after
an event or immediately after a four clock synchronization
period.
Indirect addressing is used to access the gain profile RAM,
the I coefficients RAM and the Q coefficients RAM. This type
of access relies on loading the RAM data into direct address
0x14 and the RAM address into direct address 0x15. After a
four clock synchronization period of the decoded address
0x15, the contents of the RAM data register is moved to the
address pointed to by the RAM address register. The µP can
perform back-to-back accesses to the RAM data register and
RAM address register, but must maintain four f_CLK periods
between accesses to the same address. This limits the
maximum µP access rate for the RAM to
104MHz/4 = 26MHz. The RAM address register defines a
16-bit address space that is partitioned into pages of 256
words by indirect address <9:8>. Indirect address<15>
determines the access type, 1 = read; 0 = write.
The address map and bit field details for the microprocessor
interface is shown in the Tables 10-47. The procedures for
reading and writing to this interface are provided below.
Microprocessor Read/Write Procedure
The QPUC offers the microprocessor read/write access to all
of the configuration working registers, the gain profile RAM,
the I coefficients RAM and the Q coefficients RAM.
RDMODE determines the read/write mode for the
microprocessor interface as detailed in the pin description
table. The following examples have RDMODE set low, which
configures the interface for separate RD and WR strobes.
Configuration Read/Write Procedure
Write Access to the Configuration Master
Registers
Perform a direct write to the configuration master registers
by setting up the address A<6:0>, data P<15:0>, and
generating WR strobe. The overall configuration loading
sequence is as shown. The order of writing to the device
should be maintained as:
1. Write the Main Control register 0x0c. 0x9000 sets the
immediate update and microprocessor hold bits.
2. Write Device Control 0x78, bit 0 to set the broadcast bit if
writing to multiple channels. Set to 0 when writing to a
single channel.
3. Write all remaining registers sequentially.
4. Load all filter and gain coefficients.
5. Repeat steps 2-4 for all channels.
6. Write control word 0x0c to the final configuration values.
RDMODE
RD
WR
A<6:0>
0xc 0x78 0x2 0x3 0x4 0x5
P<15:0>
9000
FIGURE 17. CONFIGURATION WRITE TRANSFER
Read Access to the Configuration Slave Registers
1. Perform a direct read of a configuration register by
dropping the RD line low to transfer data from the register
selected by A<6:0> onto the data bus P<15:0>.
RDMODE
RD
WR
A<6:0>
0XC 0X78 0X2 0X3 0X4 0X5
P<15:0> ^HI-Z
DATA VALID
FIGURE 18. CONFIGURATION READ TRANSFER
I/Q Sample Read/Write Procedure
Write Access to the I/Q Sample Master Registers
2. Enable the parallel input format by clearing bit 15 of the
Serial control register, 0x11.
3. Perform a direct write to Control word 1 by setting up the
address A<6:0>, data P<15:0>, and generating a rising
edge on WR.
4. Perform a direct write to Control word 0 by setting up the
address A<6:0>, data P<15:0>, and generating a rising
edge on WR. A write strobe transfers the contents of the
I/Q master registers to the first location of the FIFO.
5. Wait 4 clock cycles before performing the next write to the
Q data master register.
Read Access to the I/Q Sample Slave Registers
1. Perform a direct read of the I slave register by dropping
the RD line low to transfer data from the slave register
selected by A<6:0> onto the data bus P<15:0>.
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