ISL5217 Datasheet, PDF (37/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
TABLE 42. I AND Q CHANNEL COEFFICIENTS (15:0)
BIT
15:0
NOTES:
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x300-0x3ff (PAGE 3)
FUNCTION
DESCRIPTION
Filter coefficient
256 location RAM. Use this page when the I and Q coefficients are the same.
Coefficients RAM Read/Write Procedure (2’s complement format only)
Write access to the Coefficient RAMs when I equal Q:
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM data to location 0x14 with the coefficient.
3. Load the RAM write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the RAM location
specified by the contents of the register at location 0x15. (Indirect address[15] =0, Indirect address[9:8]=”11”).
4. Wait 4 clock cycles before performing the next write to the RAM data register.
5. Repeat steps 2-4.
6. Return RAM control back to the channel by disabling the µP hold mode.
Read access to the Q Coefficient RAM:
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the RAM read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register
at location 0x15 onto the read bus. (Indirect address[15] =1, Indirect address[9:8]=”11”).
3. Wait 4 clock cycles before performing the next write to the RAM address register.
4. After all data has been loaded, return RAM control back to the channel by disabling the µP hold mode.
TABLE 43. TXENX CONTROL
INDIRECT
ADDRESS
0x400
0x401
0x402
0x403
0x404 -
0x406
0x407
NOTES:
TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x400-0x407 (PAGE 4)
FUNCTION
TXENX Cycle 0 Low
TXENX Cycle 0 High
TXENX Cycle 1 Low
TXENX Cycle 1 High
Reserved
TXENX cycle 0 low time count <15:0>.
TXENX cycle 0 high time count <15:0>.
TXENX cycle 1 low time count <15:0>.
TXENX cycle 1 high time count <15:0>.
Not Used.
DESCRIPTION
TXENX Cycle Lengths FSRMode<1:0>, cycle 1 length<4:0>, cycle 0 length<4:0>
FSRMode affects what is output on the channel FSRX pin, but only if TXENX control, control word 0x0c, bit 11 is set to one. The FSRMode<1:0> is
defined as:
00 No change to FSRX output.
01 No change to FSRX output.
10 FSR = internal channel UPDX.
11 FSR = internal channel TXENX. TXENX SIB control (0x0c, bit 3) must be set when FSRMode 11 is utilized, otherwise a TXENX glitch will be
observed on the rising edge of TXENX.
To start the TXENX cycle function following a reset, the user must provide a normal channel update via one of the 2 possible update mechanisms
(software or hardware). An update also resets all of the TXENX counters and starts the device up in cycle 0 with TXENX high.
Write access to the TXENX cycle controls:
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the data to location 0x14.
3. Load the indirect write address to location 0x15. A write strobe transfers the contents of the register at location 0x14 into the location specified
by the contents of the register at location 0x15. (Indirect address[15] =0).
4. Assert the write strobe again to update the configuration register.
5. Wait 4 clock cycles before performing the next write to the data register.
6. Repeat steps 2-5.
7. Return control back to the channel by disabling the µP hold mode.
Read access to the TXENX cycle controls:
Care should be utilized to only read registers back immediately after writing since loading indirect addr 0x15 with 040X causes 0x040X to get
loaded with indirect register 0x14’s contents.
1. Enable the µP hold mode by setting bit 12 of the Main Control register 0x0c.
2. Load the read address to location 0x15. A read strobe transfers the contents of the RAM location specified by the contents of the register at
location 0x15 onto the read bus. (Indirect address[15] =1).
3. Wait 4 clock cycles before performing the next write to the address register.
4. Return control back to the channel by disabling the µP hold mode.
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