ISL5217 Datasheet, PDF (32/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
TABLE 30. UPDATE MASK (Continued)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0e
BIT
FUNCTION
DESCRIPTION
5
Sample Rate Divider
4
Sample Rate Freq
3
Sample Fine Phase
2
Sample Coarse Phase
1
Routing Control
0
I Strobe
1 = Update, 0 = No Update.
NOTES:
25. The mask register enables the slave registers to be updated from a hardware or software strobe.
26. The mask register is not used when µP is updating a configuration slave register immediately.
27. There is no immediate update on the I strobe.
28. Update mask <1> only affects the top routing control nibble for this channel.
BIT
FUNCTION
15:2 Reserved
1
Soft Reset
(Channel Reset)
0
Software Update
(General Update)
TABLE 31. IMMEDIATE ACTION
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0f
DESCRIPTION
Not used
Soft reset. Self clearing pulse zeroes FIFO’s, zeroes data RAMs, and clears all but the master registers.
The device will reload the slave configuration registers on the next TX enable or update strobe
Software update Self clearing pulse allows µP write to load all configuration slave registers synchronously
as determined by the update mask. The software equivalent of the hardware Update strobe
BIT
FUNCTION
15:4 Reserved
3
Tx Enable Polarity
2
Update Polarity
1
FSR Polarity
0
Serial CLK Polarity
TABLE 32. POLARITY CONTROL
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x10
DESCRIPTION
N/A
TX enable polarity
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
0=
1=
Update polarity.
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
0=
1=
Frame strobe polarity.
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
0=
1=
Serial clk polarity.
0 = defines an assertion as a transition from a logic low to a logic high
1 = defines an assertion as a transition from a logic high to a logic low
0=
1=
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