ISL24201_14 Datasheet, PDF (8/12 Pages) Intersil Corporation – Programmable VCOM Calibrator with EEPROM

ISL24201
Table 1 shows the calculated results of the V_COM voltage with
these values.
TABLE 1. EXAMPLE V_OUT vs REGISTER VALUE
REGISTER VALUE
0
V_OUT (V)
8.49
20
8.34
40
8.18
60
8.02
80
7.87
100
7.71
120
7.55
127
7.50
140
7.40
160
7.24
180
7.09
200
6.93
220
6.77
240
6.62
255
6.50
Figure 6 is used to find the minimum saturation voltage for an
I_OUT maximum of 100µA, which is about 0.3V. The minimum
V_OUT is 6.5V, which also meets the minimum V_OUT - V_SET
requirements specified in Equation 14:
V_OUTMIN
=
6.5 V
>
1_----5_----V_--
20
+
0.3 V
=
1.05 V
(EQ. 14)
OUT Pin Leakage Current
When the voltage on the OUT pin is greater than 10V, there is a
leakage current flowing into the pin in addition to the I_SET
current. Figure 9 shows the I_SET current and the OUT pin current
for OUT pin voltage up to 19V. In applications where the voltage
on the OUT pin will be greater than 10V, the actual output voltage
will be lower than the voltage calculated by Equation 6. The
graph in Figure 9 was measured with R_SET = 4.99kΩ.
OUT and SET Pin Current vs. OUT Pin Voltage
Register = 255
0.300
0.250
OUT Pin Current
0.200
SET Pin Current
0.150
0.100
0.050
0.000
0.0
2.0
4.0
6.0
8.0
10.0 12.0 14.0 16.0 18.0 20.0
OUT Pin Voltage (V)
FIGURE 9. OUT PIN LEAKAGE CURRENT
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 10. When applying power, V_DD should be applied before or
at the same time as A_VDD. The minimum time for t_VS is 0µs.
When removing power, the sequence of V_DD and A_VDD is not
important.
V_DD
A_VDD
t_VS
FIGURE 10. POWER SUPPLY SEQUENCE
Do not remove V_DD or A_VDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
Operating and Programming
Supply Voltage and Current
To program the EEPROM, A_VDD must be ≥10.8V. If programming
is not required, the ISL24201 will operate over an A_VDD range of
4.5V to 19V.
During EEPROM programming, I_DD and I_AVDD will temporarily be
higher than their quiescent currents. Figure 11 shows a typical
I_DD and I_AVDD current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 12. The algorithm
allows up to 4 erase cycles and 4 programming cycles, however
typical parts only require 1 cycle of each, sometimes 2 when
A_VDD is near the minimum 10.8V limit.
8
FN7586.1
December 9, 2010