ISL24201_14 Datasheet, PDF (6/12 Pages) Intersil Corporation – Programmable VCOM Calibrator with EEPROM

ISL24201
DCP (Digitally Controlled Potentiometer)
Figure 4 shows the relationship between the register value and
the resistor string of the DCP. Note that the register value of zero
actually selects the first step of the resistor string. The output
voltage of the DCP is given by Equation 1:
V_DCP
=
⎛
⎝
R_-----e_---g_----i_--s_---t_---e_-2--r_-5--V_--6-a_----l_--u_----e_----+-----1_{--⎠⎞}
⎛
⎝
A_{----2V----D0---D--⎠⎞}
(EQ. 1)
A_VDD
A_VDD
20
19R
R
REGISTER
VALUE
255
254
253
252
251
2
1
0
V_DCP
FIGURE 4. SIMPLIFIED SCHEMATIC OF DIGITAL CONTROL
POTENTIOMETER (DCP)
Output Current Sink
Figure 5 shows the schematic of the OUT pin current sink. The
circuit made up of amplifier A1, transistor Q1, and resistor R_SET
forms a voltage controlled current source.
AVDD
AVDD
VDCP
A1
OUT
R1
VOUT
Q1
R2
VSAT
SET
VSET = (IOUT)*(RSET) = VDCP
IOUT
RSET
FIGURE 5. CURRENT SINK CIRCUIT
The maximum value of I_OUT can be calculated by substituting the
maximum register value of 255 into Equation 2, resulting in
Equation 3:
I_OUT(MAX)
=
----^A----^V---^D----^D-----
20 R _{S E T}
(EQ. 3)
Equation 2 can also be used to calculate the unit sink current
step size by removing the Register Value term from it as shown in
Equation 4.
I_STEP
=
-----------------^A---^V----^D---^D------------------
( 256 ) ( 20 ) ( R _{S E T} )
(EQ. 4)
The voltage difference between the OUT pin and SET pin, which are
also the drain and source of the output transistor, should be greater
than the minimum saturation voltage for the I_OUT(MAX) being used.
This will keep the output transistor in its saturation region to
maintain linear operation over the full range of register values.
Figure 6 shows I_DS vs V_DS for transistor Q1. The line labeled
"Minimum Saturation Voltage" is the minimum voltage that should
be maintained across the drain and source of Q1. To find the
minimum saturation voltage for a specific condition, locate the
voltage at the intersection of the I_OUT(MAX) value from Equation 3
and the line labeled "Minimum Saturation Voltage".
4.5
MINIMUM SATURATION
4.0 VOLTAGE
3.5
SATURATION REGION
3.0
2.5
2.0
1.5
1.0
0.5
0
0 1 2 3 4 5 6 7 8 9 10
VDS (V)
FIGURE 6. I_DS vs V_DS FOR THE ISL24201 OUTPUT TRANSISTOR
The external R_SET resistor sets the full-scale sink current that
determines the lowest output voltage of the external voltage divider
R₁ and R₂. I_OUT is calculated as shown by Equation 2:
I_OUT
=
V_{----D----C---P--}
R_SET
=
⎛
⎝
R_-----e_---g_----i_--s_---t_---e_-2--r_-5--V_--6-a_----l_--u_----e_----+-----1_{--⎠⎞}
⎛
⎝
A_{----2V----D0---D--⎠⎞}
⎛
⎝
-_R----_S¹---_E---_T-_⎠⎞
(EQ. 2)
6
FN7586.1
December 9, 2010