FN4496 Datasheet, PDF (8/14 Pages) Intersil Corporation – Advanced PWM and Dual Linear Power Control

HIP6017
sets the fault latch. A comparator indicates when C_SS is
fully charged (UP signal), such that an under-voltage event
on either linear output (FB2 or FB3) is ignored until after
the soft-start interval (T4 in Figure 6). At start-up, this
allows V_OUT2 and V_OUT3 to slew up without generating a
fault. Cycling the bias input voltage (+12V_IN on the VCC
pin) off then on resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V_OUT1 to increase. When the output exceeds the
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on as required in order to regulate V_OUT1 to 1.15 x
DACOUT. This blows the input fuse and reduces V_OUT1.
The fault latch raises the FAULT/RT pin close to VCC
potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V_OUT1 is
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on as
needed to regulate V_OUT1 to 1.26V.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r_DS(ON) to monitor the current for protection
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an over-
current condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB2 and FB3 for under-voltage to protect
against excessive currents.
Figures 8 and 9 illustrate the over-current protection with
an overload on OUT1. The overload is applied at T0 and
the current increases through the output inductor (L_OUT1).
At time T1, the OVER-CURRENT1 comparator trips when
the voltage across Q1 (I_D • r_DS(ON)) exceeds the level
programmed by R_OCSET. This inhibits all outputs,
discharges the soft-start capacitor (C_SS) with a 11mA
current sink, and increments the counter. C_SS recharges at
T2 and initiates a soft-start cycle with the error amplifiers
clamped by soft-start. With OUT1 still overloaded, the
inductor current increases to trip the over-current
comparator. Again, this inhibits all outputs, but the soft-start
voltage continues increasing to 4V before discharging. The
counter increments to 2. The soft-start cycle repeats at T3
and trips the over-current comparator. The SS pin voltage
increases to 4V at T4 and the counter increments to 3. This
sets the fault latch to disable the converter. The fault is
reported on the FAULT/RT pin.
10V
0V
COUNT
=1
4V
FAULT
REPORTED
COUNT
=2
COUNT
=3
2V
0V
OVERLOAD
APPLIED
0A
T0 T1
T2
T3
T4
TIME
FIGURE 8. OVER-CURRENT OPERATION
The linear regulator operates in the same way as PWM1 to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause FB2 or FB3 to fall
below the linear under-voltage threshold, the LUV signal
sets the over-current latch if C_SS is fully charged. Blanking the
LUV signal during the C_SS charge interval allows the linear
outputs to build above the under-voltage threshold during
normal start-up. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistor R_OCSET1 programs the over-current trip level for the
PWM converter. As shown in Figure 9, the internal 200µA
current sink develops a voltage across R_OCSET (V_SET) that is
referenced to V_IN. The DRIVE signal enables the over-current
comparator (OVER-CURRENT1). When the voltage across
the upper MOSFET (V_DS(ON)) exceeds V_SET, the over-
current comparator trips to set the over-current latch. Both
V_SET and V_DS are referenced to V_IN and a small capacitor
across R_OCSET helps V_OCSET track the variations of V_IN due
to MOSFET switching. The over-current function will trip at a
peak inductor current (I_PEAK) determined by:
I_PEAK = ^I---^O----^C----^S----^E_r---_D-^T---_S--^×--₍--_O-^R---_N-^O---₎--^C----^S----^E---^T--
The OC trip point varies with MOSFET’s temperature. To
avoid over-current tripping in the normal operating load
range, determine the R_OCSET resistor from the equation
above with:
1. The maximum r_DS(ON) at the highest junction temperature.
2. The minimum I_OCSET from the specification table.
3. Determine I_PEAK for I_PEAK > I_OUT(MAX) + (∆I) / 2, where
∆I is the output inductor ripple current.
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