FN4496 Datasheet, PDF (13/14 Pages) Intersil Corporation – Advanced PWM and Dual Linear Power Control

HIP6017
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The HIP6017 requires 3 N-Channel power MOSFETs. Two
MOSFETs are used in the synchronous-rectified buck
topology of the PWM converter. The linear controller drives a
MOSFET as a pass transistor. These should be selected
based upon r_DS(ON) , gate supply requirements, and thermal
management requirements.
PWM1 MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction loss is the only component of power
dissipation for the lower MOSFET. Only the upper MOSFET
has switching losses, since the lower device turns on into
near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET’s body diode. The gate-
charge losses are proportional to the switching frequency
(F_S) and are dissipated by the HIP6017, thus not
contributing to the MOSFETs’ temperature rise. However,
large gate charge increases the switching interval, t_SW
which increases the upper MOSFET switching losses.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
P_UPPER = ^I--^O-----²----^×-----^r--^D----^S----_V⁽--^O--_I--_N-^N----⁾---^×-----^V-----^O----^U----^T-- + ^I---^O-----^×-----^V----^I--^N-----^×-₂----^t--^S----^W------^×-----^F----^S--
P_LOWER = ^I---^O----²----^×-----^r--^D----^S----⁽---^O----^N---_V-⁾---^×-_I-_N---⁽---^V----^I--^N-----–----^V-----^O----^U-----^T---⁾
The r_DS(ON) is different for the two previous equations even
if the type device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 14 shows the gate drive where the
upper gate-to-source voltage is approximately V_CC less the
input supply. For +5V main power and +12VDC for the bias,
the gate-to-source voltage of Q1 is 7V. The lower gate drive
voltage is +12VDC. A logic-level MOSFET is a good choice
for Q1 and a logic-level MOSFET can be used for Q2 if its
absolute gate-to-source voltage rating exceeds the
maximum voltage applied to V_CC.
+12V
V_CC
HIP6017
UGATE
PHASE
-
LGATE
+
PGND
GND
+5V OR LESS
Q1
NOTE:
V_GS ≈ V_CC -5V
Q2
CR1
NOTE:
V_GS ≈ V_CC
FIGURE 14. OUTPUT GATE DRIVERS
Rectifier CR1 is a clamp that catches the negative inductor
voltage swing during the dead time between the turn off of
the lower MOSFET and the turn on of the upper MOSFET.
The diode must be a Schottky type to prevent the lossy
parasitic MOSFET body diode from conducting. It is
acceptable to omit the diode and let the body diode of the
lower MOSFET clamp the negative inductor swing, but
efficiency might drop one or two percent as a result. The
diode's rated reverse breakdown voltage must be greater
than twice the maximum input voltage.
Linear Controller MOSFET Selection
The main criteria for selection of MOSFET for the linear
regulator is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
P_LINEAR = I_O × (V_IN – V_OUT)
Select a package and heatsink that maintains the junction
temperature below the maximum rating while operating at
the highest expected ambient temperature.
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