FN4496 Datasheet, PDF (7/14 Pages) Intersil Corporation – Advanced PWM and Dual Linear Power Control

HIP6017
drives an external MOSFET (Q3) to supply the GTL bus
power (V_OUT3).
Initialization
The HIP6017 automatically initializes upon receipt of input
power. By the time the soft-start (SS) voltage reaches 4V,
the 3.3V input has to be high enough such that the two linear
outputs (V_OUT2, V_OUT3) have exceeded their under-voltage
threshold. A typical ATX supply meets this requirement. The
Power-On Reset (POR) function continually monitors the
input supply voltages. The POR monitors the bias voltage
(+12V_IN) at the VCC pin and the 5V input voltage (+5V_IN) at
the OCSET1 pin. The normal level on OCSET1 is equal to
+5V_IN less a fixed voltage drop (see over-current
protection). The POR function initiates soft-start operation
after both input supply voltages exceed their POR
thresholds.
Soft-Start
The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the soft-start interval). Then an internal
11µA current source charges an external capacitor (C_SS) on
the SS pin to 4V. The PWM error amplifier reference input
(+ terminal) and output (COMP1 pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
ramps from 1V to 4V, the output clamp allows generation of
PHASE pulses of increasing width that charge the output
capacitor(s). After this initial stage, the reference input clamp
slows the output voltage rate-of-rise and provides a smooth
transition to the final set voltage. Additionally, both linear
regulator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
Figure 6 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse-width on the PHASE pin
increases. The interval of increasing pulse-width continues
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the 2.0V
output (V_OUT1) in Figure 6, this time occurs at T2. During
the interval between T2 and T3, the error amplifier reference
ramps to the final value and the converter regulates the
output to a voltage proportional to the SS pin voltage. At T3
the input clamp voltage exceeds the reference voltage and
the output voltage is in regulation.
The remaining outputs are also programmed to follow the
SS pin voltage. Each linear output (V_OUT2 and V_OUT3)
initially follows a ramp similar to that of the PWM output.
When each output reaches sufficient voltage the input
reference clamp slows the rate of output voltage rise. The
PGOOD
(2V/DIV)
0V
SOFT-START
(1V/DIV)
0V
OUTPUT
VOLTAGES
(0.5V/DIV)
V_OUT2 ( = 2.5V)
V_OUT1 (DAC = 2V)
V_OUT3 ( = 1.5V)
0V
T0 T1
T2
T3
T4
TIME
FIGURE 6. SOFT-START INTERVAL
PGOOD signal toggles ‘high’ when all output voltage levels
have exceeded their under-voltage levels. See the Soft-Start
Interval section under Applications Guidelines for a
procedure to determine the soft-start interval.
Fault Protection
All three outputs are monitored and protected against
extreme overload. A sustained overload on any linear
regulator output or an over-voltage on the PWM output
disables all converters and drives the FAULT/RT pin to VCC.
LUV
OC1
0.15V +
-
SS
+
4V ^-
OV
OVER
CURRENT
LATCH
SQ
INHIBIT
R
S
COUNTER
R
FAULT _VCC
LATCH
UP
SQ
POR
R
FAULT
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
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