FN4496 Datasheet, PDF (11/14 Pages) Intersil Corporation – Advanced PWM and Dual Linear Power Control

HIP6017
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at F_LC and a zero at F_ESR. The DC gain of the modulator is
simply the input voltage, V_IN , divided by the peak-to-peak
oscillator voltage, ∆V_OSC.
Modulator Break Frequency Equations
F_LC=
-------------------¹--------------------
2π × L_O × C_O
F_ESR= ₂----_π-----_×-----_E----_S--¹---_R------_×-----_C----_O--
The compensation network consists of the error amplifier
internal to the HIP6017 and the impedance networks Z_IN
and Z_FB . The goal of the compensation network is to provide
a closed loop transfer function with an acceptable 0dB
crossing frequency (f_0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f_0dB and 180 degrees. The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
F_Z1 = ₂----_π-----_×-----_R---¹--₂-----_×----_C-----₁--
F_Z2 = ₂----_π-----_×-----₍---_R----₁-----+-¹----_R-----₃----₎---_×-----_C-----₃-
F_P1
=
--------------------------¹----------------------------
2π
×
R₂
×


CC_-----11_-----×_+-----CC_-----22_{--}
F_P2 = ₂----_π-----_×-----_R---¹--₃----_×-----_C-----₃--
Figure 12 shows an asymptotic plot of the DC-DC
converter’s gain vs frequency. The actual modulator gain
has a peak due to the high Q factor of the output filter at F_LC,
which is not shown in Figure 12. Using the above guidelines
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier. The closed loop
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
100
F_Z1 F_Z2 F_P1 F_P2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 ^(R2^/R1⁾
0
MODULATOR
-20
GAIN
20LOG
(V_IN/∆V_OSC)
COMPENSATION
GAIN
-40
F_LC
F_ESR
CLOSED LOOP
GAIN
-60
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth loop. A
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output
capacitor to filter the current ripple. The linear regulator is
internally compensated and requires an output capacitor that
meets the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and ESL
(effective series inductance) parameters rather than actual
capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor’s ESR value is related to
220