FN4496 Datasheet, PDF (10/14 Pages) Intersil Corporation – Advanced PWM and Dual Linear Power Control

HIP6017
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying the full load current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET (and/or parallel Schottky
diode). Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. Contact Intersil for evaluation
board drawings of the component placement and printed
circuit board.
There are two sets of critical components in a DC-DC
converter using a HIP6017 controller. The power
components are the most critical because they switch large
amounts of energy. The critical small signal components
connect to sensitive nodes or supply critical bypassing
current.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors and
the power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C_SS. Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node because the internal current source is only 11µA.
A multi-layer printed circuit board is recommended.
Figure 10 shows the connections of the critical components
in the converter. Note that capacitors CIN and COUT could
each represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring. The wiring traces
from the control IC to the MOSFET gate and source should
be sized to carry 1A currents. The traces for OUT2 need
only be sized for 0.2A. Locate C_OUT2 close to the HIP6017
IC.
PWM Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller. Apply the methods and
considerations to both PWM controllers.
+5V_IN
+3.3V_IN
C_IN
Q3
V_OUT3
V_OUT2
+12V
C_VCC
C_OCSET1
VCC GND
VIN2 _OCSET1
R_OCSET1
Q1
GATE3UGATE1
PHASE1
Q2
HIP6018
VOUT2 _LGATE1
L_{OUT1 VOUT1}
C_OUT1
CR1
SS PGND
C_SS
C_OUT2
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The reference
voltage level is the DAC output voltage for the PWM
controller. The error amplifier output (V_E/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V_IN at the PHASE node.
The PWM wave is smoothed by the output filter (L_O and C_O).
∆V_OSC
OSC
PWM
COMP
-
+
DRIVER
DRIVER
Z_FB
V_E/A
-
Z_IN
+
ERROR
AMP
REFERENCE
V_IN
L_O
V_OUT
PHASE
C_O
ESR
(PARASITIC)
DETAILED FEEDBACK COMPENSATION
C2
C1 R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
-
FB
+
HIP6017
REFERENCE
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
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