X9271_14 Datasheet, PDF (7/18 Pages) Intersil Corporation – Single, Digitally Controlled Potentiometer

X9271
Device Description
Instructions
Five of the eight instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register: Read the current wiper
position of the potentiometer.
• Write Wiper Counter Register: Change current wiper
position of the potentiometer.
• Read Data Register: Read the contents of the selected
Data Register.
• Write Data Register: Write a new value to the selected
Data Register.
• Read Status: This command returns the contents of the
WIP bit, which indicates if the internal write cycle is in
progress.
See Table 8 for details of the instruction set.
The basic sequence of the 3-byte instruction is shown in
Figure 2. These 3-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a
Data Register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper position. The
response of the wiper to this action is delayed by t_WRL. A
transfer from the WCR (current wiper position) to a Data
Register is a write to nonvolatile memory and takes a
minimum of t_WR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers, or it may occur globally, where the
transfer occurs between all potentiometers and one
associated register. The Read Status Register instruction is
the only unique format (Figure 3).
Two instructions require a 2-byte sequence to complete
(Figure 4). These instructions transfer data between the host
and the X9271; either between the host and one of the data
registers, or directly between the host and the Wiper
Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register:
Transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• XFR Wiper Counter Register to Data Register:
Transfers the contents of the specified Wiper Counter
Register to the associated Data Register.
The final command is Increment/Decrement
(Figures 5 and 6). It is different from the other commands,
because its length is indeterminate. Once the command is
issued, the master can clock the selected wiper up and/or
down in one resistor segment step, thereby providing a fine-
tuning capability to the host. For each SCK clock pulse
(t_HIGH) while SI is HIGH, the selected wiper moves one
resistor segment towards the R_H terminal. Similarly, for each
SCK clock pulse while SI is LOW, the selected wiper moves
one resistor segment towards the R_L terminal.
Write-in-Process (WIP) Bit
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
the Write-in-Process bit (WIP). The WIP bit is read with a
Read Status command.
CS
SCL
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 0 0 A1 A0
Device ID
Internal
Address
I3 I2 I1 I0 RB RA P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Instruction
Opcode
Register Pot/BankWCR[7:0] valid only when P1 = P0 = 0;
Address ^Address
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
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FN8174.4
July 18, 2014